packet_status_block.vhd

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
LIBRARY ipbus_lib;
USE ipbus_lib.ipbus.all;
LIBRARY infrastructure_lib;
use infrastructure_lib.packet_mux_type.all;
 
ENTITY packet_status_block IS
    GENERIC(
        TOB_FIFO_ADDR_MAX_WIDTH: positive := 12;
        MERGED_FIFO_ADDR_MAX_WIDTH: positive := 11;
        RAW_FIFO_ADDR_MAX_WIDTH: positive := 11;
        MAX_PACKET_WIDTH    : positive := 8
    );
    PORT (
-- clocks etc
    clk_320 : in std_logic;
    rst_320 : in std_logic;
    clk_ipb : in std_logic;
    rst_ipb : in std_logic;
    bcr_320 : in std_logic;
    ecr_320 : in std_logic;
--  upstream IPBus
    ipb_in  : in ipb_wbus;
    ipb_out : out ipb_rbus;
--  MGT TOB input spy RAMs
    ipbus_tob_mgt_wbus_array        : out ipb_wbus_array(3 downto 0);   -- array of wbus
    ipbus_tob_mgt_rbus_array        : in ipb_rbus_array(3 downto 0);    -- array of rbus
--  MGT raw input spy RAMs
    ipbus_raw_mgt_wbus_array        : out ipb_wbus_array(3 downto 0);
    ipbus_raw_mgt_rbus_array        : in ipb_rbus_array(3 downto 0);
--  Merger debug spy RAMs
    ipbus_merger_spy_wbus_array     : out ipb_wbus_array(1 downto 0);
    ipbus_merger_spy_rbus_array     : in ipb_rbus_array(1 downto 0);
--  Aurora output spy RAMs
    ipbus_built_fifo_wbus_array     : out ipb_wbus_array(1 downto 0);
    ipbus_built_fifo_rbus_array     : in ipb_rbus_array(1 downto 0);
 
--  MGT TOB input spy RAM control
    rst_ipbus_tob_mgt_addr_bus      : out std_logic_vector(3 downto 0); -- size of spy RAM 16-bit address
    ipbus_tob_mgt_wraparound_bus    : out std_logic_vector(3 downto 0);
--  MGT raw input spy RAM control
    rst_ipbus_raw_mgt_addr_bus      : out std_logic_vector(3 downto 0);
    ipbus_raw_mgt_wraparound_bus    : out std_logic_vector(3 downto 0);
--  Merger debug spy RAM control
    rst_ipbus_merger_spy_addr_bus   : out std_logic_vector(1 downto 0);
    ipbus_merger_spy_wraparound_bus : out std_logic_vector(1 downto 0);
--  Aurora output spy RAM control
    rst_ipbus_built_fifo_addr_bus   : out std_logic_vector(1 downto 0);
    ipbus_built_fifo_wraparound_bus : out std_logic_vector(1 downto 0);
--  Readout delay control
    readout_delay                   : out std_logic_vector(31 downto 0);
--  TOB MGT status
    tob_mgt_packet_received_bus     : in std_logic_vector(3 downto 0);
    tob_mgt_safe_mode_bus           : in std_logic_vector(3 downto 0);
    tob_mgt_packet_err_bus          : in std_logic_vector(3 downto 0);
    tob_mgt_length_err_bus          : in std_logic_vector(3 downto 0);
    tob_mgt_bcn_err_bus             : in std_logic_vector(3 downto 0);
    tob_mgt_last_l1id_bus           : in mgt_data_array(3 downto 0);
 
--  Raw MGT status
    raw_mgt_packet_received_bus     : in std_logic_vector(3 downto 0);
    raw_mgt_safe_mode_bus           : in std_logic_vector(3 downto 0);
    raw_mgt_packet_err_bus          : in std_logic_vector(3 downto 0);
    raw_mgt_length_err_bus          : in std_logic_vector(3 downto 0);
    raw_mgt_last_l1id_bus           : in mgt_data_array(3 downto 0);
 
--  TOB FIFO status block A -- TOB FIFOs have same values, XOFF & BUSY
    tob_fifo_fill_level_A_bus       : in fifo_status_array(3 downto 0); -- array of 16-bits
    tob_packet_count_A_bus          : in fifo_status_array(3 downto 0); -- array of 16-bits
    tob_fifo_error_A_bus            : in std_logic_vector(3 downto 0);  -- status to be read by IPBus (if rd & wr pointers crash) to be counted.
 
--  TOB FIFO status block B  XOFF & BUSY
    tob_fifo_fill_level_B_bus       : in fifo_status_array(3 downto 0);
    tob_packet_count_B_bus          : in fifo_status_array(3 downto 0);
    tob_fifo_error_B_bus            : in std_logic_vector(3 downto 0);
 
--  L1A status
    Last_L1ID_merger_A              : in std_logic_vector(31 downto 0); -- ECRID and L1ID
    Last_L1ID_merger_B              : in std_logic_vector(31 downto 0);
    L1A_seen_bus                    : in std_logic_vector(1 downto 0);  -- Merger A (0), Merger B (1)
 
--  TOB merging counts per Processor FPGA
    TOB_packet_merged_A_bus         : in std_logic_vector(3 downto 0);
    TOB_packet_missing_A_bus        : in std_logic_vector(3 downto 0);
    debug_packet_created_A_bus      : in std_logic_vector(3 downto 0);
    TOB_packet_merged_B_bus         : in std_logic_vector(3 downto 0);
    TOB_packet_missing_B_bus        : in std_logic_vector(3 downto 0);
    debug_packet_created_B_bus      : in std_logic_vector(3 downto 0);
 
--  MUX status
    mux_active_bus                  : in std_logic_vector(1 downto 0);
    mux_l1id_valid_bus              : in std_logic_vector(1 downto 0);
    mux_source_bus                  : in std_logic_vector(7 downto 0);
    mux_l1id_bus                    : in mgt_data_array(1 downto 0);
 
-- status bits  PAUSE
    merged_fifo_fill_level_A_bus    : in fifo_status_array(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1) 16-bits inputs
    merged_packet_count_A_bus       : in fifo_status_array(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1) 16-bits
    merged_fifo_error_A_bus         : in std_logic_vector(1 downto 0);  -- merged TOB FIFO (0), debug FIFO (1) count errors
 
-- status bits  PAUSE
    merged_fifo_fill_level_B_bus    : in fifo_status_array(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1)
    merged_packet_count_B_bus       : in fifo_status_array(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1)
    merged_fifo_error_B_bus         : in std_logic_vector(1 downto 0);  -- merged TOB FIFO (0), debug FIFO (1)
 
--  Raw FIFO status block  XOFF & BUSY
    raw_fifo_fill_level_bus         : in fifo_status_array(3 downto 0); -- 16-bits
    raw_packet_count_bus            : in fifo_status_array(3 downto 0);
    raw_fifo_error_bus              : in std_logic_vector(3 downto 0);
 
--  MGT flow control
    tob_mgt_xoff_bus                : out std_logic_vector(3 downto 0); -- to process FPGA
    raw_mgt_xoff_bus                : out std_logic_vector(3 downto 0);
--  BUSY control
    tob_busy_bus                    : out std_logic_vector(3 downto 0);
    raw_busy_bus                    : out std_logic_vector(3 downto 0);
--  Merging block flow control
    Block_A_pause                   : out std_logic_vector(1 downto 0);
    Block_B_pause                   : out std_logic_vector(1 downto 0)
    );
END packet_status_block;
 
architecture Behavioral of packet_status_block is
    signal counter_control_i            : std_logic_vector(31 downto 0);
    signal spy_ram_rst_wr_addr_i        : std_logic_vector(31 downto 0);
    signal wraparound_enable_i          : std_logic_vector(31 downto 0);
 
    signal rst_err_cntrs_i          : std_logic ; -- reset all memory error counters
    signal rst_status_cntrs_i       : std_logic ; -- reset all status counters
    signal rst_xoff_cntr_i          : std_logic ; -- reset all BUSY/xoff counters
 
    signal tob_fifo_err_cnt_A_bus_i     : mgt_data_array(3 downto 0);   -- 32-bit error counter
    signal tob_fifo_err_cnt_B_bus_i     : mgt_data_array(3 downto 0);   -- 32-bit error counter
    signal raw_fifo_err_cnt_i           : mgt_data_array(3 downto 0);   -- 32-bit error counter
    signal merged_fifo_err_cnt_A_bus_i  : mgt_data_array(1 downto 0); -- 32-bit error counter
    signal merged_fifo_err_cnt_B_bus_i  : mgt_data_array(1 downto 0); -- 32-bit error counter
 
    signal tob_fifo_prog_full_thresh_assert_i    : std_logic_vector(15 downto 0);   -- 16-b out of 32-b register
    signal tob_fifo_prog_full_thresh_negate_i    : std_logic_vector(15 downto 0);   -- 16-b out of 32-b register
    signal raw_fifo_prog_full_thresh_assert_i    : std_logic_vector(15 downto 0);   -- 16-b out of 32-b register
    signal raw_fifo_prog_full_thresh_negate_i    : std_logic_vector(15 downto 0);   -- 16-b out of 32-b register
 
    signal tob_fifo_xoff_thresh_assert_i    : std_logic_vector(15 downto 0);    -- 16-b out of 32-b register
    signal tob_fifo_xoff_thresh_negate_i    : std_logic_vector(15 downto 0);    -- 16-b out of 32-b register
    signal merged_fifo_xoff_thresh_assert_i : std_logic_vector(15 downto 0);    -- 16-b out of 32-b register
    signal merged_fifo_xoff_thresh_negate_i : std_logic_vector(15 downto 0);    -- 16-b out of 32-b register
    signal raw_fifo_xoff_thresh_assert_i    : std_logic_vector(15 downto 0);    -- 16-b out of 32-b register
    signal raw_fifo_xoff_thresh_negate_i    : std_logic_vector(15 downto 0);    -- 16-b out of 32-b register
    signal dbg_fifo_xoff_thresh_assert_i    : std_logic_vector(15 downto 0);    -- 16-b out of 32-b register
    signal dbg_fifo_xoff_thresh_negate_i    : std_logic_vector(15 downto 0);    -- 16-b out of 32-b register
 
    signal fifo_bc_count_i: std_logic_vector(31 downto 0);
    signal tob_busy_cnt_32b_A_i, tob_busy_active_cnt_32b_A_i, tob_busy_assert_cnt_32b_A_i: mgt_data_array(3 downto 0);  -- 32-b register
    signal tob_busy_cnt_32b_B_i, tob_busy_active_cnt_32b_B_i, tob_busy_assert_cnt_32b_B_i: mgt_data_array(3 downto 0);  -- 32-b register
    signal tob_xoff_cnt_32b_A_i, tob_xoff_active_cnt_32b_A_i, tob_xoff_assert_cnt_32b_A_i: mgt_data_array(3 downto 0);  -- 32-b register
    signal tob_xoff_cnt_32b_B_i, tob_xoff_active_cnt_32b_B_i, tob_xoff_assert_cnt_32b_B_i: mgt_data_array(3 downto 0);  -- 32-b register
    signal raw_busy_cnt_32b_i, raw_busy_active_cnt_32b_i, raw_busy_assert_cnt_32b_i : mgt_data_array(3 downto 0);   -- 32-b register
    signal raw_xoff_cnt_32b_i, raw_xoff_active_cnt_32b_i, raw_xoff_assert_cnt_32b_i : mgt_data_array(3 downto 0);   -- 32-b register
    signal merged_xoff_cnt_32b_A_i, merged_xoff_active_cnt_32b_A_i, merged_xoff_assert_cnt_32b_A_i: mgt_data_array(1 downto 0); -- 32-b register
    signal merged_xoff_cnt_32b_B_i, merged_xoff_active_cnt_32b_B_i, merged_xoff_assert_cnt_32b_B_i: mgt_data_array(1 downto 0); -- 32-b register
 
-- tide mark status registers
    signal tob_fifo_tide_mark_A_bus_i   : fifo_status_array(3 downto 0);    -- array of 16-bits
    signal tob_packet_tide_mark_A_bus_i : fifo_status_array(3 downto 0);    -- array of 16-bits
    signal tob_fifo_tide_mark_B_bus_i   : fifo_status_array(3 downto 0);    -- array of 16-bits
    signal tob_packet_tide_mark_B_bus_i : fifo_status_array(3 downto 0);    -- array of 16-bits
    signal merged_fifo_tide_mark_A_bus_i    : fifo_status_array(1 downto 0);    -- array of 16-bits
    signal merged_packet_tide_mark_A_bus_i  : fifo_status_array(1 downto 0);    -- array of 16-bits
    signal merged_fifo_tide_mark_B_bus_i    : fifo_status_array(1 downto 0);    -- array of 16-bits
    signal merged_packet_tide_mark_B_bus_i  : fifo_status_array(1 downto 0);    -- array of 16-bits
    signal raw_fifo_tide_mark_bus_i     : fifo_status_array(3 downto 0);    -- array of 16-bits
    signal raw_packet_tide_mark_bus_i   : fifo_status_array(3 downto 0);    -- array of 16-bits
 
    signal TOB_packet_merged_cnt_A_bus_out_i    : mgt_data_array(3 downto 0);   -- 32-b register
    signal TOB_packet_missing_cnt_A_bus_out_i   : mgt_data_array(3 downto 0);   -- 32-b register
    signal debug_packet_created_cnt_A_bus_out_i : mgt_data_array(3 downto 0);   -- 32-b register
    signal TOB_packet_merged_cnt_B_bus_out_i    : mgt_data_array(3 downto 0);   -- 32-b register
    signal TOB_packet_missing_cnt_B_bus_out_i   : mgt_data_array(3 downto 0);   -- 32-b register
    signal debug_packet_created_cnt_B_bus_out_i : mgt_data_array(3 downto 0);   -- 32-b register
 
    signal Last_L1ID_merger_A_i, Last_L1ID_merger_B_i : std_logic_vector(31 downto 0);
    signal L1A_cnt_merger_A_i, L1A_cnt_merger_B_i : std_logic_vector(31 downto 0);
 
    signal tob_mgt_packet_received_cnt_bus_i : mgt_data_array(3 downto 0);  -- 32-b register
    signal tob_mgt_safe_mode_cnt_bus_i : mgt_data_array(3 downto 0);    -- 32-b register
    signal tob_mgt_packet_err_cnt_bus_i : mgt_data_array(3 downto 0);   -- 32-b register
    signal tob_mgt_length_err_cnt_bus_i : mgt_data_array(3 downto 0);   -- 32-b register
    signal tob_mgt_bcn_err_cnt_bus_i : mgt_data_array(3 downto 0);  -- 32-b register
 
    signal raw_mgt_packet_received_cnt_bus_i : mgt_data_array(3 downto 0);  -- 32-b register
    signal raw_mgt_safe_mode_cnt_bus_i : mgt_data_array(3 downto 0);    -- 32-b register
    signal raw_mgt_packet_err_cnt_bus_i : mgt_data_array(3 downto 0);   -- 32-b register
    signal raw_mgt_length_err_cnt_bus_i : mgt_data_array(3 downto 0);   -- 32-b register
 
    signal tob_mgt_last_l1id_bus_i, raw_mgt_last_l1id_bus_i: mgt_data_array(3 downto 0);
    signal tob_mgt_last_error_l1id_bus_i, raw_mgt_last_error_l1id_bus_i: mgt_data_array(3 downto 0);
 
    signal mux_l1id_valid_bus_i: std_logic_vector(1 downto 0);
    signal mux_l1id_bus_i: mgt_data_array(1 downto 0);
    signal mux_source_bus_i: std_logic_vector(7 downto 0);
    signal mux_source_a, mux_source_b: integer range 0 to 15 := 0;
    signal mux_a_pkt_bus_i, mux_b_pkt_bus_i: std_logic_vector(5 downto 0);
    signal mux_a_pkt_cnt_bus_i, mux_b_pkt_cnt_bus_i: mgt_data_array(5 downto 0);
    signal mux_a_last_l1id_bus_i, mux_b_last_l1id_bus_i: mgt_data_array(5 downto 0) := (Others => (Others => '0'));
    signal mux_active_bus_i: fifo_status_array(1 downto 0);
    signal mux_a_active_bus_i, mux_b_active_bus_i: fifo_status_array(5 downto 0);
    signal mux_a_active_tide_mark_bus_i, mux_b_active_tide_mark_bus_i: fifo_status_array(5 downto 0);
    signal mux_orbit_active_bus_i, mux_orbit_active_tide_mark_bus_i: fifo_status_array(1 downto 0);
 
BEGIN
 
    rst_ipbus_tob_mgt_addr_bus      <= spy_ram_rst_wr_addr_i(3 downto 0);
    rst_ipbus_raw_mgt_addr_bus      <= spy_ram_rst_wr_addr_i(7 downto 4);
    rst_ipbus_built_fifo_addr_bus   <= spy_ram_rst_wr_addr_i(9 downto 8);
    rst_ipbus_merger_spy_addr_bus   <= spy_ram_rst_wr_addr_i(11 downto 10);
    ipbus_tob_mgt_wraparound_bus    <= wraparound_enable_i(3 downto 0);
    ipbus_raw_mgt_wraparound_bus    <= wraparound_enable_i(7 downto 4);
    ipbus_built_fifo_wraparound_bus <= wraparound_enable_i(9 downto 8);
    ipbus_merger_spy_wraparound_bus <= wraparound_enable_i(11 downto 10);
 
    rst_err_cntrs_i     <= counter_control_i(4) or rst_320;
    rst_status_cntrs_i  <= counter_control_i(5) or rst_320;
    rst_xoff_cntr_i     <= counter_control_i(6) or rst_320;
 
L1ID_latch: process(clk_320)
begin
    if (rising_edge(clk_320)) then
        if (rst_status_cntrs_i = '1') then
            Last_L1ID_merger_A_i <= (Others => '0');
            Last_L1ID_merger_B_i <= (Others => '0');
            for i in 3 downto 0 loop
                tob_mgt_last_l1id_bus_i(i) <= (Others => '0');
                tob_mgt_last_error_l1id_bus_i(i) <= (Others => '0');
                raw_mgt_last_l1id_bus_i(i) <= (Others => '0');
                raw_mgt_last_error_l1id_bus_i(i) <= (Others => '0');
            end loop;
        else
            if (L1A_seen_bus(0) = '1') then
                Last_L1ID_merger_A_i <= Last_L1ID_merger_A;
            end if;
            if (L1A_seen_bus(1) = '1') then
                Last_L1ID_merger_B_i <= Last_L1ID_merger_B;
            end if;
            for i in 3 downto 0 loop
                if (tob_mgt_packet_received_bus(i) = '1') then
                    tob_mgt_last_l1id_bus_i(i) <= tob_mgt_last_l1id_bus(i);
                end if;
                if (tob_mgt_packet_err_bus(i) = '1') or (tob_mgt_length_err_bus(i) = '1') then
                    tob_mgt_last_error_l1id_bus_i(i) <= tob_mgt_last_l1id_bus(i);
                end if;
                if (raw_mgt_packet_received_bus(i) = '1') then
                    raw_mgt_last_l1id_bus_i(i) <= raw_mgt_last_l1id_bus(i);
                end if;
                if (raw_mgt_packet_err_bus(i) = '1') or (raw_mgt_length_err_bus(i) = '1') then
                    raw_mgt_last_error_l1id_bus_i(i) <= raw_mgt_last_l1id_bus(i);
                end if;
            end loop;
        end if;
    end if;
end process L1ID_latch;
 
MUX_source_block: process(clk_320)
variable pkt_active_a, pkt_active_b : unsigned(18 downto 0);
constant max_count: unsigned(18 downto 0) := (Others => '1');
variable last_src_a, last_src_b: std_logic_vector(3 downto 0);
begin
    if (rising_edge(clk_320)) then
        if (rst_status_cntrs_i = '1') then
            pkt_active_a := (Others => '0');
            pkt_active_b := (Others => '0');
            last_src_a := (Others => '0');
            last_src_b := (Others => '0');
        else
            if (mux_l1id_valid_bus(0) = '1') or (mux_source_bus(3 downto 0) /= last_src_a) then
                pkt_active_a := (Others => '0');
            elsif (mux_active_bus(0) = '1') and (pkt_active_a < max_count) then
                pkt_active_a := pkt_active_a + 1;
            end if;
            last_src_a := mux_source_bus(3 downto 0);
            if (mux_l1id_valid_bus(1) = '1') or (mux_source_bus(7 downto 4) /= last_src_b) then
                pkt_active_b := (Others => '0');
            elsif (mux_active_bus(1) = '1') and (pkt_active_b < max_count) then
                pkt_active_b := pkt_active_b + 1;
            end if;
            last_src_b := mux_source_bus(7 downto 4);
        end if;
-- Convert from 320 MHz to BC...
        mux_active_bus_i(0) <= std_logic_vector(pkt_active_a(18 downto 3));
        mux_active_bus_i(1) <= std_logic_vector(pkt_active_b(18 downto 3));
-- and register all these for the mux_sig_gen...
        mux_l1id_valid_bus_i <= mux_l1id_valid_bus;
        mux_l1id_bus_i <= mux_l1id_bus;
        mux_source_bus_i <= mux_source_bus;
    end if;
end process MUX_source_block;
 
mux_source_a <= to_integer(unsigned(mux_source_bus_i(3 downto 0)));
mux_source_b <= to_integer(unsigned(mux_source_bus_i(7 downto 4)));
 
mux_sig_gen: for i in 5 downto 0 generate
begin
    mux_a_bus_block: process(clk_320)
    begin
        if (rising_edge(clk_320)) then
            if (rst_status_cntrs_i = '1') then
                mux_a_last_l1id_bus_i(i) <= (Others => '0');
            elsif (mux_source_a = i) then
                mux_a_pkt_bus_i(i) <= mux_l1id_valid_bus_i(0);
                mux_a_active_bus_i(i) <= mux_active_bus_i(0);
                if (mux_l1id_valid_bus_i(0) = '1') then
                    mux_a_last_l1id_bus_i(i) <= mux_l1id_bus_i(0);
                end if;
            else
                mux_a_pkt_bus_i(i) <= '0';
                mux_a_active_bus_i(i) <= (Others => '0');
            end if;
        end if;
    end process mux_a_bus_block;
 
    mux_b_bus_block: process(clk_320)
    begin
        if (rising_edge(clk_320)) then
            if (rst_status_cntrs_i = '1') then
                mux_b_last_l1id_bus_i(i) <= (Others => '0');
            elsif (mux_source_b = i) then
                mux_b_pkt_bus_i(i) <= mux_l1id_valid_bus_i(1);
                mux_b_active_bus_i(i) <= mux_active_bus_i(1);
                if (mux_l1id_valid_bus_i(1) = '1') then
                    mux_b_last_l1id_bus_i(i) <= mux_l1id_bus_i(1);
                end if;
            else
                mux_b_pkt_bus_i(i) <= '0';
                mux_b_active_bus_i(i) <= (Others => '0');
            end if;
        end if;
    end process mux_b_bus_block;
end generate;
 
MUX_orbit_block: process(clk_320)
variable orbit_active_a, orbit_active_b, last_orbit_active_a, last_orbit_active_b : unsigned(16 downto 0);
begin
    if (rising_edge(clk_320)) then
        if (rst_status_cntrs_i = '1') then
            orbit_active_a := (Others => '0');
            orbit_active_b := (Others => '0');
            last_orbit_active_a := (Others => '0');
            last_orbit_active_b := (Others => '0');
        elsif (bcr_320 = '1') then
            last_orbit_active_a := orbit_active_a;
            last_orbit_active_b := orbit_active_b;
            orbit_active_a := (Others => '0');
            orbit_active_b := (Others => '0');
        else
            if (mux_active_bus(0) = '1') then
                orbit_active_a := orbit_active_a + 1;
            end if;
            if (mux_active_bus(1) = '1') then
                orbit_active_b := orbit_active_b + 1;
            end if;
        end if;
        mux_orbit_active_bus_i(0) <= "00" & std_logic_vector(last_orbit_active_a(16 downto 3));
        mux_orbit_active_bus_i(1) <= "00" & std_logic_vector(last_orbit_active_b(16 downto 3));
    end if;
end process MUX_orbit_block;
 
-- Readout_ipb_slave Module is responsible for communication with IPBus.
U1_rdout_ipb_slave : entity infrastructure_lib.rdout_ipb_slave
    GENERIC map (
        TOB_FIFO_MAX_ADDR_WIDTH => TOB_FIFO_ADDR_MAX_WIDTH,
        MERGED_FIFO_MAX_ADDR_WIDTH => MERGED_FIFO_ADDR_MAX_WIDTH,
        RAW_FIFO_MAX_ADDR_WIDTH => RAW_FIFO_ADDR_MAX_WIDTH,
        PACKET_MAX_WIDTH => MAX_PACKET_WIDTH
    )
    Port map (
        clk_320     => clk_320  ,   -- i/p
        ipb_rst     => rst_ipb  ,   -- i/p
        ipb_clk     => clk_ipb  ,   -- i/p
        IPb_in      => IPb_in  ,    -- i/p
        IPb_out     => IPb_out ,    -- o/p
 
        ipbus_out_tob_mgt_wbus_array => ipbus_tob_mgt_wbus_array ,  -- o/p
        ipbus_in_tob_mgt_rbus_array  => ipbus_tob_mgt_rbus_array ,  -- i/p
        ipbus_out_raw_mgt_wbus_array => ipbus_raw_mgt_wbus_array ,  -- o/p
        ipbus_in_raw_mgt_rbus_array  => ipbus_raw_mgt_rbus_array ,  -- i/p
        ipbus_out_merger_spy_wbus_array => ipbus_merger_spy_wbus_array,
        ipbus_in_merger_spy_rbus_array  => ipbus_merger_spy_rbus_array,
        ipbus_out_built_fifo_wbus_array => ipbus_built_fifo_wbus_array ,    -- o/p
        ipbus_in_built_fifo_rbus_array  => ipbus_built_fifo_rbus_array ,        -- i/p
-- control registers output
        bcr_320             => bcr_320,
        ecr_320             => ecr_320,
        readout_delay       => readout_delay,
        counter_control     => counter_control_i,
        spy_ram_rst_wr_addr => spy_ram_rst_wr_addr_i,  -- o/p
        wraparound_enable   => wraparound_enable_i,    -- o/p
-- BUSY_FIFO_CONTROL
        tob_fifo_prog_full_thresh_assert    => tob_fifo_prog_full_thresh_assert_i,  -- o/p
        tob_fifo_prog_full_thresh_negate    => tob_fifo_prog_full_thresh_negate_i,  -- o/p
        raw_fifo_prog_full_thresh_assert    => raw_fifo_prog_full_thresh_assert_i,  -- o/p
        raw_fifo_prog_full_thresh_negate    => raw_fifo_prog_full_thresh_negate_i,  -- o/p
-- XOFF_FIFO_CONTROL
        tob_fifo_xoff_thresh_assert     => tob_fifo_xoff_thresh_assert_i,  -- o/p
        tob_fifo_xoff_thresh_negate     => tob_fifo_xoff_thresh_negate_i,  -- o/p
        raw_fifo_xoff_thresh_assert     => raw_fifo_xoff_thresh_assert_i,  -- o/p
        raw_fifo_xoff_thresh_negate     => raw_fifo_xoff_thresh_negate_i,  -- o/p
        merged_fifo_xoff_thresh_assert  => merged_fifo_xoff_thresh_assert_i,  -- o/p
        merged_fifo_xoff_thresh_negate  => merged_fifo_xoff_thresh_negate_i,  -- o/p
        dbg_fifo_xoff_thresh_assert     => dbg_fifo_xoff_thresh_assert_i,  -- o/p
        dbg_fifo_xoff_thresh_negate     => dbg_fifo_xoff_thresh_negate_i,  -- o/p
--  MGT status blocks
        tob_mgt_packet_received_cnt_bus => tob_mgt_packet_received_cnt_bus_i,
        tob_mgt_safe_mode_cnt_bus       => tob_mgt_safe_mode_cnt_bus_i,
        tob_mgt_packet_err_cnt_bus      => tob_mgt_packet_err_cnt_bus_i,
        tob_mgt_length_err_cnt_bus      => tob_mgt_length_err_cnt_bus_i,
        tob_mgt_bcn_err_cnt_bus         => tob_mgt_bcn_err_cnt_bus_i,
        tob_mgt_last_l1id_bus           => tob_mgt_last_l1id_bus_i,
        tob_mgt_last_error_l1id_bus     => tob_mgt_last_error_l1id_bus_i,
        raw_mgt_packet_received_cnt_bus => raw_mgt_packet_received_cnt_bus_i,
        raw_mgt_safe_mode_cnt_bus       => raw_mgt_safe_mode_cnt_bus_i,
        raw_mgt_packet_err_cnt_bus      => raw_mgt_packet_err_cnt_bus_i,
        raw_mgt_length_err_cnt_bus      => raw_mgt_length_err_cnt_bus_i,
        raw_mgt_last_l1id_bus           => raw_mgt_last_l1id_bus_i,
        raw_mgt_last_error_l1id_bus     => raw_mgt_last_error_l1id_bus_i,
-- FIFO status registers
        tob_fifo_fill_level_A_bus       => tob_fifo_fill_level_A_bus ,  -- i/p
        tob_packet_count_A_bus          => tob_packet_count_A_bus ,     -- i/p
        tob_fifo_err_cnt_A_bus          => tob_fifo_err_cnt_A_bus_i ,    -- i/p
        tob_fifo_fill_level_B_bus       => tob_fifo_fill_level_B_bus,   -- i/p
        tob_packet_count_B_bus          => tob_packet_count_B_bus,          -- i/p
        tob_fifo_err_cnt_B_bus          => tob_fifo_err_cnt_B_bus_i ,      -- i/p
        merged_fifo_fill_level_A_bus    => merged_fifo_fill_level_A_bus,    -- i/p
        merged_packet_count_A_bus       => merged_packet_count_A_bus,      -- i/p
        merged_fifo_err_cnt_A_bus       => merged_fifo_err_cnt_A_bus_i ,    -- i/p
        merged_fifo_fill_level_B_bus    => merged_fifo_fill_level_B_bus,   -- i/p
        merged_packet_count_B_bus       => merged_packet_count_B_bus,       -- i/p
        merged_fifo_err_cnt_B_bus       => merged_fifo_err_cnt_B_bus_i,    -- i/p
        raw_fifo_fill_level_bus         => raw_fifo_fill_level_bus,     -- i/p
        raw_packet_count_bus            => raw_packet_count_bus,           -- i/p
        raw_fifo_err_cnt_bus            => raw_fifo_err_cnt_i,              -- i/p
-- tide mark status registers
        tob_fifo_tide_mark_A_bus        => tob_fifo_tide_mark_A_bus_i,  -- i/p
        tob_packet_tide_mark_A_bus      => tob_packet_tide_mark_A_bus_i,     -- i/p
        tob_fifo_tide_mark_B_bus        => tob_fifo_tide_mark_B_bus_i,   -- i/p
        tob_packet_tide_mark_B_bus      => tob_packet_tide_mark_B_bus_i,            -- i/p
        merged_fifo_tide_mark_A_bus     => merged_fifo_tide_mark_A_bus_i,   -- i/p
        merged_packet_tide_mark_A_bus   => merged_packet_tide_mark_A_bus_i,      -- i/p
        merged_fifo_tide_mark_B_bus     => merged_fifo_tide_mark_B_bus_i,   -- i/p
        merged_packet_tide_mark_B_bus   => merged_packet_tide_mark_B_bus_i,     -- i/p
        raw_fifo_tide_mark_bus          => raw_fifo_tide_mark_bus_i,        -- i/p
        raw_packet_tide_mark_bus        => raw_packet_tide_mark_bus_i,           -- i/p
-- Merger status registers
        Last_L1ID_merger_A              => Last_L1ID_merger_A_i,    -- ECRID and L1ID
        Last_L1ID_merger_B              => Last_L1ID_merger_B_i,
        L1A_cnt_merger_A                => L1A_cnt_merger_A_i,
        L1A_cnt_merger_B                => L1A_cnt_merger_B_i,
        TOB_packet_merged_cnt_A_bus     => TOB_packet_merged_cnt_A_bus_out_i ,  -- i/p 32-bits
        TOB_packet_missing_cnt_A_bus    => TOB_packet_missing_cnt_A_bus_out_i ,
        debug_packet_created_cnt_A_bus  => debug_packet_created_cnt_A_bus_out_i ,
        TOB_packet_merged_cnt_B_bus     => TOB_packet_merged_cnt_B_bus_out_i ,
        TOB_packet_missing_cnt_B_bus    => TOB_packet_missing_cnt_B_bus_out_i ,
        debug_packet_created_cnt_B_bus  => debug_packet_created_cnt_B_bus_out_i ,
--  MUX status blocks
        mux_orbit_active_bus            => mux_orbit_active_bus_i,
        mux_orbit_active_tide_mark_bus  => mux_orbit_active_tide_mark_bus_i,
        mux_a_active_bus                => mux_a_active_bus_i,
        mux_b_active_bus                => mux_b_active_bus_i,
        mux_a_active_tide_mark_bus      => mux_a_active_tide_mark_bus_i,
        mux_b_active_tide_mark_bus      => mux_b_active_tide_mark_bus_i,
        mux_a_pkt_cnt_bus               => mux_a_pkt_cnt_bus_i,
        mux_b_pkt_cnt_bus               => mux_b_pkt_cnt_bus_i,
        mux_a_last_l1id_bus             => mux_a_last_l1id_bus_i,
        mux_b_last_l1id_bus             => mux_b_last_l1id_bus_i,
-- BUSY and xoff counters
        fifo_bc_count           => fifo_bc_count_i,
        tob_busy_cnt_32b_A      => tob_busy_cnt_32b_A_i,    -- i/p 32-bits
        tob_busy_cnt_32b_B      => tob_busy_cnt_32b_B_i,    -- i/p 32-bits
        tob_xoff_cnt_32b_A      => tob_xoff_cnt_32b_A_i,    -- 32-bits
        tob_xoff_cnt_32b_B      => tob_xoff_cnt_32b_B_i,    -- 32-bits
        merged_xoff_cnt_32b_A   => merged_xoff_cnt_32b_A_i, -- 32-bits
        merged_xoff_cnt_32b_B   => merged_xoff_cnt_32b_B_i, -- 32-bits
        raw_busy_cnt_32b        => raw_busy_cnt_32b_i,  -- 32-bits
        raw_xoff_cnt_32b        => raw_xoff_cnt_32b_i,  -- 32-bits
 
        tob_busy_active_cnt_32b_A   => tob_busy_active_cnt_32b_A_i, -- i/p 32-bits
        tob_busy_active_cnt_32b_B   => tob_busy_active_cnt_32b_B_i, -- i/p 32-bits
        tob_xoff_active_cnt_32b_A   => tob_xoff_active_cnt_32b_A_i, -- 32-bits
        tob_xoff_active_cnt_32b_B   => tob_xoff_active_cnt_32b_B_i, -- 32-bits
        merged_xoff_active_cnt_32b_A => merged_xoff_active_cnt_32b_A_i, -- 32-bits
        merged_xoff_active_cnt_32b_B => merged_xoff_active_cnt_32b_B_i, -- 32-bits
        raw_busy_active_cnt_32b     => raw_busy_active_cnt_32b_i,   -- 32-bits
        raw_xoff_active_cnt_32b     => raw_xoff_active_cnt_32b_i,   -- 32-bits
 
        tob_busy_assert_cnt_32b_A   => tob_busy_assert_cnt_32b_A_i, -- i/p 32-bits
        tob_busy_assert_cnt_32b_B   => tob_busy_assert_cnt_32b_B_i, -- i/p 32-bits
        tob_xoff_assert_cnt_32b_A   => tob_xoff_assert_cnt_32b_A_i, -- 32-bits
        tob_xoff_assert_cnt_32b_B   => tob_xoff_assert_cnt_32b_B_i, -- 32-bits
        merged_xoff_assert_cnt_32b_A => merged_xoff_assert_cnt_32b_A_i, -- 32-bits
        merged_xoff_assert_cnt_32b_B => merged_xoff_assert_cnt_32b_B_i, -- 32-bits
        raw_busy_assert_cnt_32b     => raw_busy_assert_cnt_32b_i,   -- 32-bits
        raw_xoff_assert_cnt_32b     => raw_xoff_assert_cnt_32b_i-- 32-bits
 
        );
 
-- Readout Error Counter block.
U2_rdout_err_cnt : entity infrastructure_lib.rdout_err_cnt
    Port map (
        rst_320     => rst_320  ,   -- i/p
        clk_320     => clk_320  ,   -- i/p
        rst_err_cntrs              => rst_err_cntrs_i,
        rst_status_cntrs           => rst_status_cntrs_i,
-- FIFO errors
        tob_fifo_error_A_bus       => tob_fifo_error_A_bus,
        tob_fifo_error_B_bus       => tob_fifo_error_B_bus,
        merged_fifo_error_A_bus    => merged_fifo_error_A_bus,
        merged_fifo_error_B_bus    => merged_fifo_error_B_bus,
        raw_fifo_error_bus         => raw_fifo_error_bus,
 
        tob_fifo_err_cnt_A_bus_out     => tob_fifo_err_cnt_A_bus_i ,
        tob_fifo_err_cnt_B_bus_out     => tob_fifo_err_cnt_B_bus_i ,
        merged_fifo_err_cnt_A_bus_out  => merged_fifo_err_cnt_A_bus_i ,
        merged_fifo_err_cnt_B_bus_out  => merged_fifo_err_cnt_B_bus_i ,
        raw_fifo_err_cnt_out           => raw_fifo_err_cnt_i,
--  TOB MGT status
        tob_mgt_packet_received_bus => tob_mgt_packet_received_bus,
        tob_mgt_safe_mode_bus       => tob_mgt_safe_mode_bus,
        tob_mgt_packet_err_bus      => tob_mgt_packet_err_bus,
        tob_mgt_length_err_bus      => tob_mgt_length_err_bus,
        tob_mgt_bcn_err_bus         => tob_mgt_bcn_err_bus,
 
        tob_mgt_packet_received_cnt_bus_out => tob_mgt_packet_received_cnt_bus_i,
        tob_mgt_safe_mode_cnt_bus_out => tob_mgt_safe_mode_cnt_bus_i,
        tob_mgt_packet_err_cnt_bus_out => tob_mgt_packet_err_cnt_bus_i,
        tob_mgt_length_err_cnt_bus_out => tob_mgt_length_err_cnt_bus_i,
        tob_mgt_bcn_err_cnt_bus_out => tob_mgt_bcn_err_cnt_bus_i,
--  Raw MGT status
        raw_mgt_packet_received_bus => raw_mgt_packet_received_bus,
        raw_mgt_safe_mode_bus       => raw_mgt_safe_mode_bus,
        raw_mgt_packet_err_bus      => raw_mgt_packet_err_bus,
        raw_mgt_length_err_bus      => raw_mgt_length_err_bus,
 
        raw_mgt_packet_received_cnt_bus_out => raw_mgt_packet_received_cnt_bus_i,
        raw_mgt_safe_mode_cnt_bus_out => raw_mgt_safe_mode_cnt_bus_i,
        raw_mgt_packet_err_cnt_bus_out => raw_mgt_packet_err_cnt_bus_i,
        raw_mgt_length_err_cnt_bus_out => raw_mgt_length_err_cnt_bus_i,
--  L1A status
        L1A_seen_bus                => L1A_seen_bus,
        L1A_cnt_merger_A            => L1A_cnt_merger_A_i,
        L1A_cnt_merger_B            => L1A_cnt_merger_B_i,
-- Merging status
        TOB_packet_merged_A_bus     => TOB_packet_merged_A_bus,
        TOB_packet_missing_A_bus    => TOB_packet_missing_A_bus,
        debug_packet_created_A_bus  => debug_packet_created_A_bus ,
        TOB_packet_merged_B_bus     => TOB_packet_merged_B_bus,
        TOB_packet_missing_B_bus    => TOB_packet_missing_B_bus,
        debug_packet_created_B_bus  => debug_packet_created_B_bus ,
 
        TOB_packet_merged_cnt_A_bus_out    => TOB_packet_merged_cnt_A_bus_out_i ,
        TOB_packet_missing_cnt_A_bus_out   => TOB_packet_missing_cnt_A_bus_out_i ,
        debug_packet_created_cnt_A_bus_out => debug_packet_created_cnt_A_bus_out_i ,
        TOB_packet_merged_cnt_B_bus_out    => TOB_packet_merged_cnt_B_bus_out_i ,
        TOB_packet_missing_cnt_B_bus_out   => TOB_packet_missing_cnt_B_bus_out_i ,
        debug_packet_created_cnt_B_bus_out => debug_packet_created_cnt_B_bus_out_i,
-- MUX status
        mux_a_pkt_bus   => mux_a_pkt_bus_i,
        mux_b_pkt_bus   => mux_b_pkt_bus_i,
 
        mux_a_pkt_cnt_bus_out => mux_a_pkt_cnt_bus_i,
        mux_b_pkt_cnt_bus_out => mux_b_pkt_cnt_bus_i
        );
 
U3_monitoring_block : entity infrastructure_lib.rdout_monitor
    Port map (
        clk_320 => clk_320,   -- i/p
        rst_xoff_cntr => rst_xoff_cntr_i,   -- i/p
        -- BUSY_FIFO_CONTROL
        tob_fifo_prog_full_thresh_assert    => tob_fifo_prog_full_thresh_assert_i,  -- i/p
        tob_fifo_prog_full_thresh_negate    => tob_fifo_prog_full_thresh_negate_i,  -- i/p
        raw_fifo_prog_full_thresh_assert    => raw_fifo_prog_full_thresh_assert_i,  -- i/p
        raw_fifo_prog_full_thresh_negate    => raw_fifo_prog_full_thresh_negate_i,  -- i/p
        -- XOFF_FIFO_CONTROL
        tob_fifo_xoff_thresh_assert    => tob_fifo_xoff_thresh_assert_i,  -- i/p
        tob_fifo_xoff_thresh_negate    => tob_fifo_xoff_thresh_negate_i,  -- i/p
        merged_fifo_xoff_thresh_assert => merged_fifo_xoff_thresh_assert_i,  -- i/p
        merged_fifo_xoff_thresh_negate => merged_fifo_xoff_thresh_negate_i,  -- i/p
        raw_fifo_xoff_thresh_assert    => raw_fifo_xoff_thresh_assert_i,  -- i/p
        raw_fifo_xoff_thresh_negate    => raw_fifo_xoff_thresh_negate_i,  -- i/p
        dbg_fifo_xoff_thresh_assert    => dbg_fifo_xoff_thresh_assert_i,  -- i/p
        dbg_fifo_xoff_thresh_negate    => dbg_fifo_xoff_thresh_negate_i,  -- i/p
        -- FIFO Fill Levels
        tob_fifo_fill_level_A_bus    => tob_fifo_fill_level_A_bus ,     -- i/p
        tob_fifo_fill_level_B_bus    => tob_fifo_fill_level_B_bus,      -- i/p
        merged_fifo_fill_level_A_bus => merged_fifo_fill_level_A_bus,   -- i/p
        merged_fifo_fill_level_B_bus => merged_fifo_fill_level_B_bus,   -- i/p
        raw_fifo_fill_level_bus      => raw_fifo_fill_level_bus,        -- i/p
 
        fifo_bc_count           => fifo_bc_count_i,
        tob_busy_cnt_32b_A      => tob_busy_cnt_32b_A_i,    -- o/p 32-bits
        tob_xoff_cnt_32b_A      => tob_xoff_cnt_32b_A_i,    -- o/p 32-bits
        tob_busy_cnt_32b_B      => tob_busy_cnt_32b_B_i,    -- o/p 32-bits
        tob_xoff_cnt_32b_B      => tob_xoff_cnt_32b_B_i,    -- o/p 32-bits
        merged_xoff_cnt_32b_A   => merged_xoff_cnt_32b_A_i, -- o/p 32-bits
        merged_xoff_cnt_32b_B   => merged_xoff_cnt_32b_B_i, -- o/p 32-bits
        raw_busy_cnt_32b        => raw_busy_cnt_32b_i,  -- 32-bits
        raw_xoff_cnt_32b        => raw_xoff_cnt_32b_i,  -- 32-bits
 
        tob_busy_active_cnt_32b_A   => tob_busy_active_cnt_32b_A_i, -- o/p 32-bits
        tob_busy_active_cnt_32b_B   => tob_busy_active_cnt_32b_B_i, -- o/p 32-bits
        tob_xoff_active_cnt_32b_A   => tob_xoff_active_cnt_32b_A_i, -- 32-bits
        tob_xoff_active_cnt_32b_B   => tob_xoff_active_cnt_32b_B_i, -- 32-bits
        merged_xoff_active_cnt_32b_A => merged_xoff_active_cnt_32b_A_i, -- 32-bits
        merged_xoff_active_cnt_32b_B => merged_xoff_active_cnt_32b_B_i, -- 32-bits
        raw_busy_active_cnt_32b     => raw_busy_active_cnt_32b_i,   -- 32-bits
        raw_xoff_active_cnt_32b     => raw_xoff_active_cnt_32b_i,   -- 32-bits
 
        tob_busy_assert_cnt_32b_A   => tob_busy_assert_cnt_32b_A_i, -- o/p 32-bits
        tob_busy_assert_cnt_32b_B   => tob_busy_assert_cnt_32b_B_i, -- o/p 32-bits
        tob_xoff_assert_cnt_32b_A   => tob_xoff_assert_cnt_32b_A_i, -- 32-bits
        tob_xoff_assert_cnt_32b_B   => tob_xoff_assert_cnt_32b_B_i, -- 32-bits
        merged_xoff_assert_cnt_32b_A => merged_xoff_assert_cnt_32b_A_i, -- 32-bits
        merged_xoff_assert_cnt_32b_B => merged_xoff_assert_cnt_32b_B_i, -- 32-bits
        raw_busy_assert_cnt_32b     => raw_busy_assert_cnt_32b_i,   -- 32-bits
        raw_xoff_assert_cnt_32b     => raw_xoff_assert_cnt_32b_i,   -- 32-bits
        -- MGT flow control =>  ,
        tob_mgt_xoff_bus => tob_mgt_xoff_bus,   -- o/p
        raw_mgt_xoff_bus => raw_mgt_xoff_bus,   -- o/p
        -- BUSY control
        tob_busy_bus => tob_busy_bus,   -- o/p
        raw_busy_bus => raw_busy_bus,   -- o/p
        -- Pause Control
        Block_A_pause => Block_A_pause, -- o/p
        Block_B_pause => Block_B_pause-- o/p
        );
 
packet_tide_mark_block: entity infrastructure_lib.packet_tide_mark_block
    generic map(
        NChannels => 46-- number of signals being monitored
    )
    port map (
        clk_320 => clk_320,
        rst_status_cntrs => rst_status_cntrs_i,
-- ensure correct mapping between instantaneous values and tide mark status registers!
        value_bus(3 downto 0) => tob_fifo_fill_level_A_bus,
        value_bus(7 downto 4) => tob_packet_count_A_bus,
        value_bus(11 downto 8) => tob_fifo_fill_level_B_bus,
        value_bus(15 downto 12) => tob_packet_count_B_bus,
        value_bus(17 downto 16) => merged_fifo_fill_level_A_bus,
        value_bus(19 downto 18) => merged_packet_count_A_bus,
        value_bus(21 downto 20) => merged_fifo_fill_level_B_bus,
        value_bus(23 downto 22) => merged_packet_count_B_bus,
        value_bus(27 downto 24) => raw_fifo_fill_level_bus,
        value_bus(31 downto 28) => raw_packet_count_bus,
        value_bus(37 downto 32) => mux_a_active_bus_i,
        value_bus(43 downto 38) => mux_b_active_bus_i,
        value_bus(45 downto 44) => mux_orbit_active_bus_i,
 
        tide_mark_bus(3 downto 0) => tob_fifo_tide_mark_A_bus_i,
        tide_mark_bus(7 downto 4) => tob_packet_tide_mark_A_bus_i,
        tide_mark_bus(11 downto 8) => tob_fifo_tide_mark_B_bus_i,
        tide_mark_bus(15 downto 12) => tob_packet_tide_mark_B_bus_i,
        tide_mark_bus(17 downto 16) => merged_fifo_tide_mark_A_bus_i,
        tide_mark_bus(19 downto 18) => merged_packet_tide_mark_A_bus_i,
        tide_mark_bus(21 downto 20) => merged_fifo_tide_mark_B_bus_i,
        tide_mark_bus(23 downto 22) => merged_packet_tide_mark_B_bus_i,
        tide_mark_bus(27 downto 24) => raw_fifo_tide_mark_bus_i,
        tide_mark_bus(31 downto 28) => raw_packet_tide_mark_bus_i,
        tide_mark_bus(37 downto 32) => mux_a_active_tide_mark_bus_i,
        tide_mark_bus(43 downto 38) => mux_b_active_tide_mark_bus_i,
        tide_mark_bus(45 downto 44) => mux_orbit_active_tide_mark_bus_i
    );
 
END Behavioral;