packet_status_block.vhd File Reference

Instantiate the readout merging and routing FIFO status and control interface to IPBus... More...

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Entities
packet_status_block	entity
	Instantiate the readout merging and routing FIFO status and control interface to IPBus... More...
Behavioral	architecture

Detailed Description

Instantiate the readout merging and routing FIFO status and control interface to IPBus...

Instantiate the readout merging and routing FIFO status and control interface to IPBus

Performs the following functions:

i) Instantiate the IPBus fabric for the various registers and the spy RAMs

There are 8 input spy RAMs, one behind each incoming MGT and similarly 2 separate output spy RAMs into the 2 Aurora links.

ii) Instantiate the control registers for the various spy RAMs

There is a bit to reset the write address pointer and a bit to control wraparound in the RAM.

iii) Instantiate the monitoring registers for the various buffering FIFOs

There are two instances of the packet merging logic (one for each Aurora link). Each of these has 4 main buffering FIFOs for the TOB data (1 for each Processing FPGA), then 2 FIFOs after the merging logic (one for the merged TOB packet, one for any debug packets).

There are also 4 buffering FIFOs for the raw packets.

Each FIFO reports its occupancy and the number of packets it contains along with an overrun status every tick.

iv) Instantiate the flow control and associated monitoring for the various buffering FIFOs

For the FIFOs after the MGT there are XOFF bits towards each Processor FPGA for its TOB link and raw link.

This should be asserted if either of the two TOB FIFOs for TOB link bit or the raw FIFO for the raw link bit is over the XOFF assert threshold and cleared if the FIFOs are below the XOFF clear threshold.

For the FIFOs after the MGT there are also BUSY bits corresponding to each Processor FPGA TOB link and raw link.

This should be asserted if either of the two TOB FIFOs for TOB link or the raw FIFO for the raw link is over the BUSY assert threshold and cleared if the FIFOs are below the BUSY clear threshold.

For the FIFOs after the merging logic there is a pause bit for each instance of the packet merging logic.

This should be asserted if either the merged TOB FIFO or the debug FIFO is over the pause assert threshold and cleared if both FIFOs are below the pause clear threshold.

Author

Saeed Taghavi

Definition in file packet_status_block.vhd.