packet_tide_mark_block.vhd

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
LIBRARY infrastructure_lib;
use infrastructure_lib.packet_mux_type.all;
 
ENTITY packet_tide_mark_block IS
    GENERIC(
        NChannels: positive := 4    -- number of signals being monitored
    );
    PORT (
        clk_320: in std_logic;
        rst_status_cntrs: in std_logic; -- reset all packet status counters
        value_bus: in fifo_status_array(NChannels - 1 downto 0);
        tide_mark_bus: out fifo_status_array(NChannels - 1 downto 0)
    );
END ENTITY packet_tide_mark_block;
 
Architecture rtl of packet_tide_mark_block is
Begin
 
tide_mark_procs: for i in 0 to NChannels - 1 generate
 
    tide_mark_block: Process(clk_320)
    Variable tide_mark: unsigned(15 downto 0);
    Begin
        if rising_edge(clk_320) then
            if (rst_status_cntrs = '1') then
                tide_mark := (Others => '0');
            elsif (tide_mark < unsigned(value_bus(i))) then
                tide_mark := unsigned(value_bus(i));
            end if;
            tide_mark_bus(i) <= std_logic_vector(tide_mark);
        end if;
    End Process tide_mark_block;
 
End generate tide_mark_procs;
 
End rtl;