mgt_buffer.vhd

Go to the documentation of this file.

 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
LIBRARY ipbus_lib;
USE ipbus_lib.ipbus.all;
 
ENTITY mgt_buffer IS
  GENERIC(
    INPUT_FPGA_NO       : std_logic_vector(1 downto 0) := "00";
    DATA_FORMAT_VERSION : std_logic_vector (2 DOWNTO 0) := "001";
    IPBUS_ADDR_WIDTH    : positive := 10;
    ILA_ENABLED         : std_logic := '0'
  );
  port (
-- Static signals
    eFEX_number         : IN std_logic_vector(7 downto 0); -- Shelf Address and eFEX number
    enable              : in std_logic;
-- data from MGT
    clk_mgt             : in std_logic;
    data_from_mgt       : in std_logic_vector(31 downto 0);
    char_is_k           : in std_logic;
    error_from_mgt      : in std_logic;
-- data to FIFO
    clk_320             : in std_logic;
    rst_320             : in std_logic;
    fifo_data           : out std_logic_vector (63 DOWNTO 0);
    fifo_valid          : out std_logic;
    fifo_last           : out std_logic;
-- status signals
    mgt_last_l1id       : out std_logic_vector (31 downto 0);
    mgt_packet_stats    : out std_logic_vector (4 downto 0);
-- interface to IPBus
    clk_ipb             : in std_logic;
    rst_ipb             : in std_logic;
    rst_ipbus_addr      : in std_logic;
    ipbus_wraparound    : in std_logic;
    ipb_in              : in ipb_wbus;
    ipb_out             : out ipb_rbus
  );
END ENTITY mgt_buffer;
 
Architecture rtl of mgt_buffer is
 
Component mgt_readout_receiver IS
  GENERIC(
    FPGA_NO: std_logic_vector(1 downto 0) := "00";
    FORMAT_VERSION: std_logic_vector (2 DOWNTO 0) := "001"
  );
  port(
    clk: in std_logic;
    rst_clk: in std_logic;
    enable: in std_logic;
-- Static information
    eFEX_number : IN std_logic_vector(7 downto 0); -- Shelf Address and eFEX number
-- data from MGT CDC FIFO
    rd_rst_busy : in STD_LOGIC;
    m_axis_tvalid : in STD_LOGIC;
    m_axis_tready : out STD_LOGIC;
    m_axis_tdata : in STD_LOGIC_VECTOR(31 DOWNTO 0);
    m_axis_tlast : in STD_LOGIC;
    m_axis_tuser : in STD_LOGIC_VECTOR(1 DOWNTO 0);
-- data to data FIFO
    data_fifo_data: out std_logic_vector(63 downto 0);
    data_fifo_valid: out std_logic := '0';
    data_fifo_last: out std_logic := '0'
  );
END Component mgt_readout_receiver;
 
Component mgt_axi_fifo
  PORT (
    wr_rst_busy : OUT STD_LOGIC;
    rd_rst_busy : OUT STD_LOGIC;
    m_aclk : IN STD_LOGIC;
    s_aclk : IN STD_LOGIC;
    s_aresetn : IN STD_LOGIC;
    s_axis_tvalid : IN STD_LOGIC;
    s_axis_tready : OUT STD_LOGIC;
    s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    s_axis_tlast : IN STD_LOGIC;
    s_axis_tuser : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    m_axis_tvalid : OUT STD_LOGIC;
    m_axis_tready : IN STD_LOGIC;
    m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    m_axis_tlast : OUT STD_LOGIC;
    m_axis_tuser : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
  );
END Component mgt_axi_fifo;
 
Component ipbus_dpram is
    generic(
        ADDR_WIDTH: positive;
        DATA_WIDTH: positive := 32
    );
    port(
        clk: in std_logic;
        rst: in std_logic;
        ipb_in: in ipb_wbus;
        ipb_out: out ipb_rbus;
        rclk: in std_logic;
        we: in std_logic := '0';
        d: in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
        q: out std_logic_vector(DATA_WIDTH - 1 downto 0);
        addr: in std_logic_vector(ADDR_WIDTH - 1 downto 0)
    );
end Component ipbus_dpram;
 
Component ila_1 is
    PORT (
        clk : IN STD_LOGIC;
        probe0 : IN STD_LOGIC_VECTOR(34 DOWNTO 0)
    );
END Component ila_1;
 
   SIGNAL char_is_k_sig, error_from_mgt_sig, s_axis_tvalid, s_axis_tlast, wr_rst_busy, wr_rst_stretch : STD_LOGIC;
   SIGNAL m_axis_tvalid, m_axis_tready, m_axis_tlast, rd_rst_busy, rd_rst_stretch : STD_LOGIC;
   SIGNAL spy_ready_valid_i, spy_last_i : STD_LOGIC;
   SIGNAL data_from_mgt_sig, s_axis_tdata, m_axis_tdata, spy_data_i : STD_LOGIC_VECTOR(31 DOWNTO 0);
   SIGNAL s_axis_tuser, m_axis_tuser, spy_user_i : STD_LOGIC_VECTOR(2 DOWNTO 0);
 
   SIGNAL fifo_data_sig : std_logic_vector (63 DOWNTO 0);
   SIGNAL fifo_valid_sig, fifo_last_sig : std_logic;
   signal mgt_packet_stats_sig: std_logic_vector (4 downto 0);
 
   SIGNAL IPBus_RAM_addr, IPBus_RAM_addr_i  : std_logic_vector(IPBUS_ADDR_WIDTH-1 downto 0);
   SIGNAL IPBus_RAM_din, IPBus_RAM_din_i    : std_logic_vector(31 DOWNTO 0);
   SIGNAL IPBus_RAM_we, IPBus_RAM_we_i      : std_logic;
 
   SIGNAL rst_mgt_sig, rst_clk320_tff : std_logic := '0';
   SIGNAL rst_mgt_n : std_logic;
   signal rst_clkmgt_tff_buf, enable_mgt_buf : std_logic_vector(1 downto 0) := (Others => '0');
 
   attribute ASYNC_REG : string;
   attribute ASYNC_REG of rst_clkmgt_tff_buf : signal is "TRUE";
   attribute ASYNC_REG of enable_mgt_buf : signal is "TRUE";
 
Begin
 
    fifo_data <= fifo_data_sig;
    fifo_valid <= fifo_valid_sig;
    fifo_last <= fifo_last_sig;
    mgt_packet_stats <= mgt_packet_stats_sig;
 
    rst_mgt_n <= not rst_mgt_sig;
 
    MGT_receiver : mgt_readout_receiver
      GENERIC MAP (
        FORMAT_VERSION  => DATA_FORMAT_VERSION,
        FPGA_NO         => INPUT_FPGA_NO
      )
      PORT MAP (
        clk             => clk_320,
        rst_clk         => rst_320,
        eFEX_number     => eFEX_number,
        enable          => enable,
    -- data from MGT CDC FIFO
        rd_rst_busy => rd_rst_stretch,
        m_axis_tvalid => m_axis_tvalid,
        m_axis_tready => m_axis_tready,
        m_axis_tdata => m_axis_tdata,
        m_axis_tlast => m_axis_tlast,
        m_axis_tuser => m_axis_tuser(1 downto 0),
    -- data to packet_fifo
        data_fifo_data  => fifo_data_sig,
        data_fifo_valid => fifo_valid_sig,
        data_fifo_last  => fifo_last_sig
      );
 
    mgt_fifo : mgt_axi_fifo
      PORT MAP (
        wr_rst_busy => wr_rst_busy,
        rd_rst_busy => rd_rst_busy,
        m_aclk => clk_320,
        s_aclk => clk_mgt,
        s_aresetn => rst_mgt_n,
        s_axis_tvalid => s_axis_tvalid,
        s_axis_tready => OPEN,
        s_axis_tdata => s_axis_tdata,
        s_axis_tlast => s_axis_tlast,
        s_axis_tuser => s_axis_tuser,
        m_axis_tvalid => m_axis_tvalid,
        m_axis_tready => m_axis_tready,
        m_axis_tdata => m_axis_tdata,
        m_axis_tlast => m_axis_tlast,
        m_axis_tuser => m_axis_tuser
      );
 
    IPbus_RAM : ipbus_dpram
      GENERIC MAP (
        ADDR_WIDTH      => IPBUS_ADDR_WIDTH,
        DATA_WIDTH      => 32
      )
      PORT MAP (
        clk             => clk_ipb,
        rst             => rst_ipb,
        ipb_in          => ipb_in,
        ipb_out         => ipb_out,
        rclk            => clk_320,
        we              => IPBus_RAM_we,
        d               => IPBus_RAM_din,
        q               => Open,
        addr            => IPBus_RAM_addr
      );
 
input_register_block: process(clk_mgt)
    begin
        if rising_edge(clk_mgt) then
            data_from_mgt_sig <= data_from_mgt
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            char_is_k_sig <= char_is_k
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            error_from_mgt_sig <= error_from_mgt
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process input_register_block;
 
mgt_input_block: process(clk_mgt)
    Variable data_valid, data_last: std_logic := '0';
    begin
        if rising_edge(clk_mgt) then
            data_last := '0';
            if (rst_mgt_sig = '1') or (wr_rst_stretch = '1') or (s_axis_tlast = '1') or (enable_mgt_buf(1) = '0') then
                data_valid := '0';
            elsif (char_is_k_sig = '1') and (data_from_mgt_sig(4 downto 0) = "11100") then
                if data_from_mgt_sig(7 downto 5) = "101" then       -- K28.5
                    data_valid := '0';
                elsif data_from_mgt_sig(7 downto 5) = "110" then    -- K28.6
                    data_last := '1';
                elsif (data_from_mgt_sig(7) = '0') and (data_from_mgt_sig(5) = '1') and (char_is_k = '0') then  -- K28.1 or 3 followed by data, start of packet!
                    data_valid := '1';
                end if;
            end if;
            s_axis_tdata <= data_from_mgt_sig
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            s_axis_tvalid <= data_valid
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            s_axis_tlast <= data_last
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            s_axis_tuser(1 downto 0) <= error_from_mgt_sig & char_is_k_sig
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process mgt_input_block;
 
input_dodgy_block: process(clk_mgt)
    variable input_length: unsigned(8 downto 0) := (Others => '0');
    variable input_dodgy, last_tvalid: std_logic := '0';
    begin
        if rising_edge(clk_mgt) then
            if (data_from_mgt_sig = data_from_mgt) and not ((data_from_mgt_sig = x"000000bc") and (char_is_k_sig = '1')) then -- duplicate data...
                input_dodgy := '1';
            else
                input_dodgy := '0';
            end if;
            if (last_tvalid = '0') then -- previous word was K28.1 or K28.3, skip over L1ID in Processor Header
                input_length := (Others => '0');
            elsif (data_from_mgt_sig(7 downto 0) = x"dc") and (char_is_k_sig = '1') and (data_from_mgt_sig(16 downto 8) /= std_logic_vector(input_length)) then -- K28.6 Processor Trailer
                input_dodgy := '1';
            else
                input_length := input_length + 1;
            end if;
            last_tvalid := s_axis_tvalid;
            s_axis_tuser(2) <= input_dodgy
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process input_dodgy_block;
 
status_block: process(clk_320)
    Variable got_l1id: std_logic := '0';
    Variable last_l1id_var: std_logic_vector(31 downto 0);
    begin
        if rising_edge(clk_320) then
            if (rst_320 = '1') then
                got_l1id := '0';
            elsif (fifo_valid_sig = '1') and (got_l1id = '0') then
                last_l1id_var := fifo_data_sig(63 downto 32);
                got_l1id := '1';
            end if;
            if (fifo_valid_sig = '1') and (fifo_last_sig = '1') then
                got_l1id := '0';
                mgt_last_l1id <= last_l1id_var
-- pragma translate_off
                after 2 ns
-- pragma translate_on
                ;
                mgt_packet_stats_sig <= fifo_data_sig(36 downto 33) & '1'
-- pragma translate_off
                after 2 ns
-- pragma translate_on
                ;
            else
                mgt_last_l1id <= (Others => '0')
-- pragma translate_off
                after 2 ns
-- pragma translate_on
                ;
                mgt_packet_stats_sig <= (Others => '0')
-- pragma translate_off
                after 2 ns
-- pragma translate_on
                ;
            end if;
        end if;
    end process status_block;
 
ipbus_ram_block: process(clk_320)
    variable ram_addr, next_addr: unsigned(IPBUS_ADDR_WIDTH-1 downto 0) := (Others => '0');
    constant max_addr: unsigned(IPBUS_ADDR_WIDTH-1 downto 0) := (Others => '1');
    constant min_addr: unsigned(IPBUS_ADDR_WIDTH-1 downto 0) := to_unsigned(1, IPBUS_ADDR_WIDTH);
    variable ram_we, endaddr_pending, we_active: std_logic;
    variable ram_data: std_logic_vector(31 downto 0);
    begin
        if rising_edge(clk_320) then
            ram_we := '0';
            ram_addr := next_addr;
            ram_data := (Others => '0');
            if (rst_320 = '1') or (rst_ipbus_addr = '1') then
                next_addr := min_addr;
                endaddr_pending := '0';
                we_active := '1';
            elsif (spy_ready_valid_i = '1') then
                ram_we := we_active;
                ram_data := spy_data_i;
                endaddr_pending := spy_last_i;
                if (next_addr = max_addr) then
                    next_addr := min_addr;
-- Disable WE if wrapping around in RAM and ipbus_wraparound not set
                    we_active := ipbus_wraparound;
                else
                    next_addr := next_addr + 1;
                end if;
            elsif (endaddr_pending = '1') then
                ram_we := we_active;
                ram_addr := (Others => '0');
                ram_data(31 downto IPBUS_ADDR_WIDTH) := (Others => '0');
                ram_data(IPBUS_ADDR_WIDTH-1 downto 0) := std_logic_vector(next_addr);
                endaddr_pending := '0';
            end if;
            IPBus_RAM_we_i <= ram_we
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            IPBus_RAM_din_i <= ram_data
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            IPBus_RAM_addr_i <= std_logic_vector(ram_addr)
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process ipbus_ram_block;
 
spy_reg_block: process(clk_320)
    begin
        if rising_edge(clk_320) then
            spy_data_i <= m_axis_tdata
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            spy_last_i <= m_axis_tlast
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            spy_ready_valid_i <= m_axis_tready and m_axis_tvalid
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            spy_user_i <= m_axis_tuser
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process spy_reg_block;
 
ila_block : if (ILA_ENABLED = '1') generate
    mgt_ila : ila_1
      PORT MAP (
        clk => clk_320,
        probe0(31 downto 0) => spy_data_i,
        probe0(32) => spy_ready_valid_i,
        probe0(33) => spy_user_i(2),
        probe0(34) => mgt_packet_stats_sig(2)
      );
end generate;
 
ipbus_ram_reg_block: process(clk_320)
    begin
        if rising_edge(clk_320) then
            IPBus_RAM_din <= IPBus_RAM_din_i
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            IPBus_RAM_addr <= IPBus_RAM_addr_i
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            IPBus_RAM_we <= IPBus_RAM_we_i
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process ipbus_ram_reg_block;
 
rst_clk320_block : process(clk_320)
    begin
        if rising_edge(clk_320) then
            if rst_320 = '1' then
-- infer a toggle flip flop in source domain
                rst_clk320_tff <= not rst_clk320_tff;
            else
                rst_clk320_tff <= rst_clk320_tff;
            end if;
        end if;
    end process rst_clk320_block;
 
rst_clkmgt_block : process(clk_mgt)
    Variable stretch: std_logic_vector(7 downto 0) := (Others => '1');
    Variable reset_done: std_logic := '0';
    begin
        if rising_edge(clk_mgt) then
            rst_clkmgt_tff_buf <= rst_clkmgt_tff_buf(0) & rst_clk320_tff;
            if ((rst_clkmgt_tff_buf(1) xor rst_clkmgt_tff_buf(0)) = '1') or (reset_done = '0') then
                stretch := (Others => '1');
                reset_done := '1';
            else
                stretch := stretch(6 downto 0) & "0";
            end if;
            rst_mgt_sig <= stretch(7)
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process rst_clkmgt_block;
 
wr_rst_stretch_block : process(clk_mgt)
    Variable stretch: std_logic_vector(7 downto 0) := (Others => '1');
    begin
        if rising_edge(clk_mgt) then
            if (wr_rst_busy = '1') or (rst_mgt_sig = '1') then
                stretch := (Others => '1');
            else
                stretch := stretch(6 downto 0) & "0";
            end if;
            wr_rst_stretch <= stretch(7)
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process wr_rst_stretch_block;
 
rd_rst_stretch_block : process(clk_320)
    Variable stretch: std_logic_vector(7 downto 0) := (Others => '1');
    begin
        if rising_edge(clk_320) then
            if (rd_rst_busy = '1') or (rst_320 = '1') then
                stretch := (Others => '1');
            else
                stretch := stretch(6 downto 0) & "0";
            end if;
            rd_rst_stretch <= stretch(7)
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process rd_rst_stretch_block;
 
enable_clkmgt_block : process(clk_mgt)
    begin
        if rising_edge(clk_mgt) then
            enable_mgt_buf <= enable_mgt_buf(0) & enable;
        end if;
    end process enable_clkmgt_block;
 
END Architecture rtl;