mgt_readout_receiver Entity Reference

Second version of packet format engine... More...

Inheritance diagram for mgt_readout_receiver:

Entities
rtl	architecture
	Second version of packet format engine... More...

Libraries
ieee
	Use standard library.

Use Clauses
std_logic_1164
numeric_std

Generics
FPGA_NO	std_logic_vector ( 1 downto 0 ) := " 00 "
FORMAT_VERSION	std_logic_vector ( 2 DOWNTO 0 ) := " 001 "

Ports
clk	in	std_logic
rst_clk	in	std_logic
enable	in	std_logic
eFEX_number	in	std_logic_vector ( 7 downto 0 )
rd_rst_busy	in	STD_LOGIC
m_axis_tvalid	in	STD_LOGIC
m_axis_tready	out	STD_LOGIC
m_axis_tdata	in	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
m_axis_tlast	in	STD_LOGIC
m_axis_tuser	in	STD_LOGIC_VECTOR ( 1 DOWNTO 0 )
data_fifo_data	out	std_logic_vector ( 63 downto 0 )
data_fifo_valid	out	std_logic := ' 0 '
data_fifo_last	out	std_logic := ' 0 '

Detailed Description

Second version of packet format engine...

Format incoming packet (Input Data or TOB) from CDC FIFO into data FIFO

Author

David Sankey

Definition at line 13 of file mgt_readout_receiver.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd