mgt_readout_receiver.vhd

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
ENTITY mgt_readout_receiver IS
  GENERIC(
    FPGA_NO: std_logic_vector(1 downto 0) := "00";
    FORMAT_VERSION: std_logic_vector (2 DOWNTO 0) := "001"
  );
  port(
    clk: in std_logic;
    rst_clk: in std_logic;
    enable: in std_logic;
-- Static information
    eFEX_number : IN std_logic_vector(7 downto 0); -- Shelf Address and eFEX number
-- data from MGT CDC FIFO
    rd_rst_busy : in STD_LOGIC;
    m_axis_tvalid : in STD_LOGIC;
    m_axis_tready : out STD_LOGIC;
    m_axis_tdata : in STD_LOGIC_VECTOR(31 DOWNTO 0);
    m_axis_tlast : in STD_LOGIC;
    m_axis_tuser : in STD_LOGIC_VECTOR(1 DOWNTO 0);
-- data to data FIFO
    data_fifo_data: out std_logic_vector(63 downto 0);
    data_fifo_valid: out std_logic := '0';
    data_fifo_last: out std_logic := '0'
  );
END ENTITY mgt_readout_receiver;
 
Architecture rtl of mgt_readout_receiver is
 
  TYPE STATE_TYPE IS (
    init,
    pause,
    waiting,
    new_packet, -- K28.1/3
    save_payload,
    tob_trailer, -- K28.2
    padding,
    corrective_trailer, -- K28.6...
    write_trailer,
    write_last
  );
 
  signal state_sig: STATE_TYPE := init;
  signal data_from_mgt_fifo_sig, data_from_mgt_fifo_buf, data_output_sig: std_logic_vector(31 downto 0);
  signal input_length_sig, output_length_sig, slice_length_sig: std_logic_vector(8 downto 0);
  signal write_block_sig, write_block_buf, we_sig, last_sig, char_is_k_sig, error_from_mgt_sig, TOB_mode_sig, TOB_trailer_OK_sig, valid_sig, valid_buf, data_fifo_valid_sig: std_logic := '0';
  signal Errors_sig: std_logic_vector(3 downto 0); -- Safe Mode, Protocol/Link, Length, TOB/xTOB BCN mismatch
  signal trailer_info_sig: std_logic_vector(11 downto 0); -- TSN, NSlice, PEMap
 
begin
 
data_fifo_valid <= data_fifo_valid_sig;
 
Input_buffer: process(clk)
  begin
    if rising_edge(clk) then
      valid_sig <= m_axis_tvalid and enable
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
      valid_buf <= valid_sig
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
      data_from_mgt_fifo_sig <= m_axis_tdata
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
      data_from_mgt_fifo_buf <= data_from_mgt_fifo_sig
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
      char_is_k_sig <= m_axis_tuser(0)
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
      error_from_mgt_sig <= m_axis_tuser(1)
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
    end if;
  end process Input_buffer;
 
Ready_block: process(clk)
  variable ready: std_logic := '0';
  begin
    if rising_edge(clk) then
      if (rst_clk = '1') or (rd_rst_busy = '1') then
        ready := '0';
      elsif (m_axis_tlast = '1') and (m_axis_tvalid = '1') then
        ready := '0';
      elsif state_sig = init then
        ready := '1';
      end if;
      m_axis_tready <= ready
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
    end if;
  end process Ready_block;
 
Output_buffer: process(clk)
  variable toggle_bit, data_valid_bit: std_logic := '0';
  variable data_buffer: std_logic_vector(63 downto 0) := (Others => '0');
  variable output_length, next_length: unsigned(7 downto 0) := (Others => '0');
  begin
    if rising_edge(clk) then
      data_valid_bit := '0';
      if we_sig = '1' then
        data_valid_bit := toggle_bit and write_block_buf;
        data_buffer := data_output_sig & data_buffer(63 downto 32);
        toggle_bit := not toggle_bit;
      elsif state_sig = waiting then
        toggle_bit := '0';
      end if;
-- Reset output length calculation on first word written as this is the packet header...
      if state_sig = new_packet then
        next_length := (Others => '0');
        output_length := (Others => '0');
      elsif (data_valid_bit = '1') then
        output_length := next_length;
        next_length := next_length + 1;
      end if;
      data_fifo_valid_sig <= data_valid_bit
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
      data_fifo_last <= last_sig
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
      data_fifo_data <= data_buffer
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
      output_length_sig <= std_logic_vector(output_length) & "0"
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
    end if;
  end process Output_buffer;
 
Input_length_block: process(clk)
  variable input_length: unsigned(8 downto 0) := (Others => '0');
  begin
    if rising_edge(clk) then
      if state_sig = new_packet then
        input_length := (Others => '0');
      elsif ((state_sig = save_payload) or (state_sig = tob_trailer)) and (valid_sig = '1') then
        input_length := input_length + 1;
      end if;
      input_length_sig <= std_logic_vector(input_length)
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
    end if;
  end process Input_length_block;
 
Slice_length_block: process(clk)
  variable slice_length: unsigned(8 downto 0) := (Others => '0');
  begin
    if rising_edge(clk) then
      if state_sig = new_packet then
        slice_length := (Others => '0');
      elsif (char_is_k_sig = '1') and (data_from_mgt_fifo_sig(7 downto 0) = x"5C") then -- Trailer Word 1...
        slice_length := (Others => '0');
      elsif valid_sig = '1' then
        slice_length := slice_length + 1;
      end if;
      slice_length_sig <= std_logic_vector(slice_length)
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
    end if;
  end process Slice_length_block;
 
Trailer_checker: process(clk)
  variable expected_length: unsigned(7 downto 0) := (Others => '0');
  variable TOB_trailer_OK, write_block: std_logic := '0';
  begin
    if rising_edge(clk) then
      if (valid_sig = '1') then
        write_block := '1';
        if (char_is_k_sig = '1') and (data_from_mgt_fifo_sig(7 downto 0) = x"5C") then -- Trailer Word 1...
-- First work out number of 64 bit words for XTOBs
          expected_length := unsigned("00" & data_from_mgt_fifo_sig(23 downto 18));
          expected_length := expected_length + unsigned(data_from_mgt_fifo_sig(17 downto 12));
-- then number of 64 bit words for even number of TOBs
          expected_length := expected_length + unsigned(data_from_mgt_fifo_sig(11 downto 10));
-- 32 bit length of TOB frame OK (expected_length*2 + 1 for 32 bit word alignment)
          if (slice_length_sig = std_logic_vector(expected_length) & '1') then
            TOB_trailer_OK := '1';
-- No single TOB so it's an empty frame - zero suppress it...
            if (data_from_mgt_fifo_sig(9) = '0') and (slice_length_sig = std_logic_vector(to_unsigned(1, 9))) then
              write_block := '0';
            end if;
-- Safe Mode and suppressed TOBs!
          elsif (data_from_mgt_fifo_sig(27) = '1') and (slice_length_sig = std_logic_vector(to_unsigned(1, 9))) then
            TOB_trailer_OK := '1';
          else
            TOB_trailer_OK := '0';
          end if;
        else
          expected_length := (Others => '0');
          TOB_trailer_OK := '0';
        end if;
      end if;
      TOB_trailer_OK_sig <= TOB_trailer_OK
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
      write_block_sig <= write_block
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
-- Register this to be in line with data_output_sig and we_sig signals
      write_block_buf <= write_block_sig
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
    end if;
  end process Trailer_checker;
 
Output_Data_engine: process(clk)
  variable data_output: std_logic_vector(31 downto 0) := (Others => '0');
  variable write_data, last, odd_length: std_logic := '0';
  variable bcn: std_logic_vector(11 downto 0);
  variable stream_id: std_logic_vector(7 downto 0);
  begin
    if rising_edge(clk) then
      data_output := (Others => '0');
      write_data := valid_buf;
      last := '0';
      case state_sig is
        when new_packet =>  -- capture BCN
          if TOB_mode_sig = '1' then
            stream_id := x"01";
          else
            stream_id := "10" & FPGA_NO & eFEX_number(3 downto 0);
          end if;
          if (valid_buf = '1') then
            data_output := FORMAT_VERSION & "0" & x"00" & data_from_mgt_fifo_buf(19 downto 8) & stream_id;
            bcn := data_from_mgt_fifo_buf(19 downto 8);
          end if;
        when save_payload | tob_trailer =>
          data_output := data_from_mgt_fifo_buf;
          odd_length := '1'; -- in case odd length packet, in which case there will be no padding for corrective trailer!
        when padding =>
          odd_length := '0'; -- padding added for corrective trailer, so encapsulated fragment has an even length...
          write_data := '1';
        when corrective_trailer =>
          data_output(31 downto 30) := "11";
          data_output(25 downto 24) := FPGA_NO;
          data_output(23 downto 12) := bcn;
          data_output(8 downto 1) := output_length_sig(8 downto 1);
          data_output(0) := odd_length; -- reflect whether padding was added or not
          write_data := '1';
        when write_trailer =>  -- first word of trailer
          data_output(31 downto 20) := trailer_info_sig;
          data_output(19 downto 12) := eFEX_number;
          data_output(8 downto 0) := output_length_sig;
          write_data := '1';
        when write_last => -- last word of trailer (encode FPGA_NO in case this ends up in debug stream...)
          if TOB_mode_sig = '1' then
            data_output(11 downto 10) := FPGA_NO;
          end if;
          data_output(4 downto 1) := Errors_sig;
          write_data := '1';
          last := '1';
        when Others =>
          write_data := '0';
      end case;
      data_output_sig <= data_output
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
      we_sig <= write_data
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
      last_sig <= last
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
    end if;
  end process Output_Data_engine;
 
State_machine: process(clk)
  variable TOB_mode, Bad_Packet, Length_Error, BCN_Error, Seen_Trailer: std_logic := '0';
  variable Errors: std_logic_vector(3 downto 0); -- Safe Mode, Protocol/Link, Length, TOB/xTOB BCN mismatch
  variable trailer_info: std_logic_vector(11 downto 0);
  variable next_state: STATE_TYPE := init;
  begin
    if rising_edge(clk) then
      if (rst_clk = '1') or (rd_rst_busy = '1') then
        next_state := init;
        TOB_mode := '0';
      else
        if error_from_mgt_sig = '1' then
          Bad_Packet := '1';
        end if;
        Case state_sig is
          When waiting =>
            Errors := (Others => '0');
            trailer_info := (Others => '0');
            Bad_Packet := '0';
            Length_Error := '0';
            Seen_Trailer := '0';
            BCN_Error := '0';
            if (valid_sig = '1') and (char_is_k_sig = '1') and (data_from_mgt_fifo_sig(7) = '0') and (data_from_mgt_fifo_sig(5 downto 0) = "111100") then
              if data_from_mgt_fifo_sig(6) = '0' then -- K28.1 not K28.3
                -- check that xTOB BCN matches and if P0 or P3 TOB BCN matches
                if (data_from_mgt_fifo_sig(23 downto 20) /= data_from_mgt_fifo_sig(11 downto 8)) or ((FPGA_NO(0) = FPGA_NO(1)) and (data_from_mgt_fifo_sig(30 downto 24) /= data_from_mgt_fifo_sig(14 downto 8))) then
                  BCN_Error := '1';
                end if;
                TOB_mode := '1';
              else
                TOB_mode := '0';
              end if;
              next_state := new_packet;
            end if;
          When new_packet =>
            if (valid_sig = '1') then
              next_state := save_payload;
            end if;
          When save_payload | tob_trailer =>
            if (state_sig = tob_trailer) and (valid_buf = '1') and (TOB_trailer_OK_sig = '0') then -- latch bad TOB trailer in multi-slice readout...
              Length_Error := '1';
            end if;
            if (valid_sig = '1') and (char_is_k_sig = '1') then
              if (data_from_mgt_fifo_sig(7 downto 0) = x"5C") then
                next_state := tob_trailer;
                Seen_Trailer := '1';
              else -- the final trailer: check for correct even length...
                if (data_from_mgt_fifo_sig(19 downto 8) /= "000" & input_length_sig) or (TOB_mode /= Seen_Trailer) or (input_length_sig(0) = '1') then
                  Length_Error := '1';
                end if;
                Errors := data_from_mgt_fifo_sig(31) & Bad_Packet & Length_Error & BCN_Error;
                if (TOB_mode = '1') then
                  trailer_info := data_from_mgt_fifo_sig(23 downto 20) & "0" & data_from_mgt_fifo_sig(26 downto 24) & x"0";
                  if (Errors /= "0000") then
                    trailer_info(to_integer(unsigned(FPGA_NO))) := '1';
                  end if;
                else
                  trailer_info := x"00" & "00" & FPGA_NO;
                end if;
                if (Bad_Packet = '0') and (Length_Error = '0') then
                  next_state := write_trailer;
                else
                  if input_length_sig(0) = '1' then -- odd length packet, skip padding in corrective trailer
                    next_state := corrective_trailer;
                  else
                    next_state := padding;
                  end if;
                end if;
              end if;
            else
              if (valid_sig = '1') then -- clear trailer seen if more data coming
                Seen_Trailer := '0';
              end if;
              next_state := save_payload;
            end if;
          When padding =>
            next_state := corrective_trailer;
          When corrective_trailer =>
            next_state := write_trailer;
          When write_trailer =>
            next_state := write_last;
          When write_last =>
            next_state := init;
          When init =>
            next_state := pause;
          When Others => -- pause...
            next_state := waiting;
        end case;
      end if;
      state_sig <= next_state
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
      TOB_mode_sig <= TOB_mode
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
      Errors_sig <= Errors
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
      trailer_info_sig <= trailer_info
-- pragma translate_off
      after 2 ns
-- pragma translate_on
      ;
    end if;
  end process State_machine;
 
end rtl;