rtl Architecture Reference

Second version of packet format engine from MGT through to formatted (sub)block... More...

Processes
input_register_block	( clk_mgt )
mgt_input_block	( clk_mgt )
input_dodgy_block	( clk_mgt )
status_block	( clk_320 )
ipbus_ram_block	( clk_320 )
spy_reg_block	( clk_320 )
ipbus_ram_reg_block	( clk_320 )
rst_clk320_block	( clk_320 )
rst_clkmgt_block	( clk_mgt )
wr_rst_stretch_block	( clk_mgt )
rd_rst_stretch_block	( clk_320 )
enable_clkmgt_block	( clk_mgt )

Components
mgt_readout_receiver	<Entity mgt_readout_receiver>
mgt_axi_fifo
ipbus_dpram
ila_1

Signals
char_is_k_sig	STD_LOGIC
error_from_mgt_sig	STD_LOGIC
s_axis_tvalid	STD_LOGIC
s_axis_tlast	STD_LOGIC
wr_rst_busy	STD_LOGIC
wr_rst_stretch	STD_LOGIC
m_axis_tvalid	STD_LOGIC
m_axis_tready	STD_LOGIC
m_axis_tlast	STD_LOGIC
rd_rst_busy	STD_LOGIC
rd_rst_stretch	STD_LOGIC
spy_ready_valid_i	STD_LOGIC
spy_last_i	STD_LOGIC
data_from_mgt_sig	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
s_axis_tdata	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
m_axis_tdata	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
spy_data_i	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
s_axis_tuser	STD_LOGIC_VECTOR ( 2 DOWNTO 0 )
m_axis_tuser	STD_LOGIC_VECTOR ( 2 DOWNTO 0 )
spy_user_i	STD_LOGIC_VECTOR ( 2 DOWNTO 0 )
fifo_data_sig	std_logic_vector ( 63 DOWNTO 0 )
fifo_valid_sig	std_logic
fifo_last_sig	std_logic
mgt_packet_stats_sig	std_logic_vector ( 4 downto 0 )
IPBus_RAM_addr	std_logic_vector ( IPBUS_ADDR_WIDTH- 1 downto 0 )
IPBus_RAM_addr_i	std_logic_vector ( IPBUS_ADDR_WIDTH- 1 downto 0 )
IPBus_RAM_din	std_logic_vector ( 31 DOWNTO 0 )
IPBus_RAM_din_i	std_logic_vector ( 31 DOWNTO 0 )
IPBus_RAM_we	std_logic
IPBus_RAM_we_i	std_logic
rst_mgt_sig	std_logic := ' 0 '
rst_clk320_tff	std_logic := ' 0 '
rst_mgt_n	std_logic
rst_clkmgt_tff_buf	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
enable_mgt_buf	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )

Attributes
ASYNC_REG	string
ASYNC_REG	signal is " TRUE "

Instantiations
mgt_receiver	mgt_readout_receiver <Entity mgt_readout_receiver>
mgt_fifo	mgt_axi_fifo
ipbus_ram	ipbus_dpram
mgt_ila	ila_1

Detailed Description

Second version of packet format engine from MGT through to formatted (sub)block...

Format incoming packet (Input Data or TOB) from MGT through to formatted output In the case of Input Data no further processing is required en route to link, in case of TOB/xTOB this is a fragment ready for merging

Author

David Sankey

Definition at line 55 of file mgt_buffer.vhd.

Member Function Documentation

input_dodgy_block()

input_dodgy_block (   clk_mgt   )

Process

catch duplicate words and length errors in recovered clock domain duplicate words are I think illegal in TOB packets but do occur in Input Data, not least the error mask when no errors...

Definition at line 281 of file mgt_buffer.vhd.

mgt_input_block()

mgt_input_block (   clk_mgt   )

Process

map data from MGT into axi fifo with tuser as error_from_mgt & char_is_k, suppressing idle words Assert data_valid from SOP until next idle frame but not before!

Definition at line 240 of file mgt_buffer.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd