efex_tob_merger.vhd

 
-- MUX TOB packets into packet engine...
--
-- Dave Sankey, April 2021
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
LIBRARY infrastructure_lib;
use infrastructure_lib.packet_mux_type.all;
 
entity efex_tob_merger is
  GENERIC(
    DATA_FORMAT_VERSION : std_logic_vector (2 DOWNTO 0) := "001";
    DELAY_DEPTH         : Integer range 0 to 15 := 15 -- Number of SRLC32E to cascade for delayed L1A strobe over and above ftm_ttc_mode delay
  );
  port (
    clk                 : in std_logic;
    rst_clk             : in std_logic;
-- eFEX number
    eFEX_number         : in std_logic_vector(7 downto 0);
-- Control signals
    ifg_duration        : IN std_logic_vector(3 downto 0);
    fpga_tob_enabled    : IN std_logic_vector(3 downto 0);
    pause               : IN std_logic_vector(1 downto 0);
-- TTC FIFO signals
    ttc_rd_en           : OUT STD_LOGIC;
    ttc_dout            : IN std_logic_vector(49 DOWNTO 0);
    ttc_fifo_empty      : IN STD_LOGIC;
-- Input pFPGA TOB packets
    input_fifo_empty    : IN std_logic_vector(3 downto 0);
    fpga_tob_data       : IN packet_data_array(3 downto 0);
    fpga_tob_valid      : IN std_logic_vector(3 downto 0);
    fpga_tob_last       : IN std_logic_vector(3 downto 0);
    fpga_tob_ready      : OUT std_logic_vector(3 downto 0);
-- Output FIFO signals
    merged_fifo_data    : OUT packet_data_array(1 downto 0);
    merged_fifo_valid   : OUT std_logic_vector(1 downto 0);
    merged_fifo_last    : OUT std_logic_vector(1 downto 0);
-- Status signals
    L1A_seen            : OUT STD_LOGIC;
    Last_L1ID_merged    : OUT std_logic_vector(31 downto 0);    -- ECRID and L1ID (Phase-I), L0ID(31 downto 0) (Phase-II)
    TOB_packet_merged_bus   : OUT std_logic_vector(3 downto 0);
    TOB_packet_missing_bus  : OUT std_logic_vector(3 downto 0);
    debug_packet_created_bus    : OUT std_logic_vector(3 downto 0)
  );
end entity efex_tob_merger;
 
architecture rtl of efex_tob_merger is
 
Component efex_tob_processer is
  GENERIC(
    DEBUG_FORMAT_VERSION    : std_logic_vector (2 DOWNTO 0) := "001"
  );
  port (
    clk                 : in std_logic;
    rst_clk             : in std_logic;
-- TTC input signals
    ttc_info            : IN std_logic_vector(49 DOWNTO 0);
    ttc_valid           : IN std_logic;
-- Input pFPGA TOB packet
    input_fifo_empty    : IN std_logic;
    input_tob_data      : IN std_logic_vector(63 downto 0);
    input_tob_valid     : IN std_logic;
    input_tob_last      : IN std_logic;
    input_tob_ready     : OUT std_logic;
-- Output FIFO signals (0 - TOB merging, 1 - debug)
    output_fifo_data    : OUT packet_data_array(1 downto 0);
    output_fifo_valid   : OUT std_logic_vector(1 downto 0);
    output_fifo_last    : OUT std_logic_vector(1 downto 0);
    output_fifo_ready   : IN std_logic_vector(1 downto 0);
-- Status signals
    TOB_packet_ready    : OUT std_logic;
    TOB_packet_to_merge : OUT std_logic;
    TOB_packet_missing  : OUT std_logic;
    debug_packet_created    : OUT std_logic
  );
end Component efex_tob_processer;
 
Component efex_packet_merger is
  generic(NSRC: positive := 4);
  port (
    clk                 : in std_logic;
    rst_clk             : in std_logic;
    packet_merger_start : in std_logic := '0';
    packet_merger_enabled  : IN std_logic_vector(NSRC-1 downto 0);
    packet_merger_source   : OUT std_logic_vector(2 downto 0);
    packet_merger_data  : IN packet_data_array(NSRC-1 downto 0);
    packet_merger_valid : IN std_logic_vector(NSRC-1 downto 0);
    packet_merger_last  : IN std_logic_vector(NSRC-1 downto 0);
    packet_merger_ready : OUT std_logic_vector(NSRC-1 downto 0);
    packet_data         : OUT std_logic_vector (63 DOWNTO 0) ;
    packet_valid        : OUT std_logic;
    packet_last         : OUT std_logic;
    packet_sub_last     : OUT std_logic;
    packet_ready        : IN std_logic
  );
end Component efex_packet_merger;
 
Component efex_packet_mux is
  generic(NSRC: positive := 4);
  port (
    clk                 : in std_logic;
    rst_clk             : in std_logic;
-- Shelf and eFEX number (for error recovery trailer)
    eFEX_number         : in std_logic_vector(7 downto 0);
    pause               : in std_logic := '0';
    packet_mux_enabled  : IN std_logic_vector(NSRC-1 downto 0);
    packet_mux_reset    : IN std_logic_vector(NSRC-1 downto 0);
    packet_mux_source   : OUT std_logic_vector(3 downto 0);
    packet_mux_data     : IN packet_data_array(NSRC-1 downto 0);
    packet_mux_valid    : IN std_logic_vector(NSRC-1 downto 0);
    packet_mux_last     : IN std_logic_vector(NSRC-1 downto 0);
    packet_mux_ready    : OUT std_logic_vector(NSRC-1 downto 0);
    packet_data         : OUT std_logic_vector (63 DOWNTO 0) ;
    packet_valid        : OUT std_logic;
    packet_last         : OUT std_logic;
    packet_ready        : IN std_logic
  );
end Component efex_packet_mux;
 
COMPONENT SRLC32E is
    generic(
        INIT     : std_logic_vector(31 downto 0) := (Others => '0')
    );
    port(
        CLK : in std_logic;
        D : in std_logic;
        CE : in std_logic;
        A : in std_logic_vector(4 downto 0);
        Q : out std_logic;
        Q31 : out std_logic
    );
end COMPONENT SRLC32E;
 
TYPE STATE_TYPE IS (
    idle,
    wait_fifos,
    start_event,
    prepare_tobs,
    start_merger,
    merge_tobs,
    ifg
);
 
signal state_sig: STATE_TYPE;
signal debug_data_bus, tob_data_bus: packet_data_array(3 downto 0);
signal debug_valid_bus, debug_last_bus, debug_ready_bus, tob_valid_bus, tob_last_bus, tob_ready_bus: std_logic_vector(3 downto 0);
signal ttc_valid_bus, tob_packet_ready_bus, tob_packet_to_merge_bus, tob_good_bus, packet_missing_bus, packet_created_bus: std_logic_vector(3 downto 0);
signal tob_packet_data_sig, tob_header_data_sig: std_logic_vector (63 downto 0);
signal ttc_read_sig, ttc_valid_sig, tob_packet_valid_sig, tob_packet_last_sig, tob_packet_sub_last_sig: std_logic;
signal tob_merger_start_sig, debug_enable_sig, debug_fifo_valid_sig, debug_fifo_last_sig: std_logic;
signal fifo_delay_start, fifo_delay_end, ifg_delay_start, ifg_delay_end: std_logic;
signal q_i: std_logic_vector(DELAY_DEPTH - 1 downto 0);
signal tob_packet_source_sig: std_logic_vector(2 downto 0);
signal dummy_sig: std_logic_vector(1 downto 0);
signal error_bus: std_logic_vector(5 downto 0);
signal merged_fifo_data_sig: packet_data_array(1 downto 0);
signal merged_fifo_valid_sig, merged_fifo_last_sig: std_logic_vector(1 downto 0);
 
 
Begin
 
TOB_sources: for i in 0 to 3 generate
 
    tob_processer: efex_tob_processer
        GENERIC map (
            DEBUG_FORMAT_VERSION => DATA_FORMAT_VERSION
        )
        port map (
            clk                 => clk,
            rst_clk             => rst_clk,
            -- TTC input signals
            ttc_info            => ttc_dout,
            ttc_valid           => ttc_valid_bus(i), -- only trigger if this FPGA is enabled...
            -- Input pFPGA TOB packet
            input_fifo_empty    => input_fifo_empty(i),
            input_tob_data      => fpga_tob_data(i),
            input_tob_valid     => fpga_tob_valid(i),
            input_tob_last      => fpga_tob_last(i),
            input_tob_ready     => fpga_tob_ready(i),
            -- Output FIFO signals (0 - TOB merging, 1 - debug)
            output_fifo_data(0) => tob_data_bus(i),
            output_fifo_data(1) => debug_data_bus(i),
            output_fifo_valid(0) => tob_valid_bus(i),
            output_fifo_valid(1) => debug_valid_bus(i),
            output_fifo_last(0) => tob_last_bus(i),
            output_fifo_last(1) => debug_last_bus(i),
            output_fifo_ready(0) => tob_ready_bus(i),
            output_fifo_ready(1) => debug_ready_bus(i),
            -- Status signals
            TOB_packet_ready    => tob_packet_ready_bus(i),
            TOB_packet_to_merge => tob_packet_to_merge_bus(i),
            TOB_packet_missing  => packet_missing_bus(i),
            debug_packet_created => packet_created_bus(i)
        );
 
End generate TOB_sources;
 
TOB_packet_missing_bus <= packet_missing_bus;
debug_packet_created_bus <= packet_created_bus;
 
-- Merge the validated TOB fragments into the TOB stream
TOB_merger : efex_packet_merger
    GENERIC MAP (
        NSRC => 6
    )
    PORT MAP (
        clk                 => clk,
        rst_clk             => rst_clk,
        packet_merger_start => tob_merger_start_sig,
        packet_merger_enabled(0) => '1',
        packet_merger_enabled(4 downto 1) => tob_good_bus,
        packet_merger_enabled(5) => '1',
        packet_merger_source => tob_packet_source_sig,
        packet_merger_data(0) => tob_header_data_sig,
        packet_merger_data(4 downto 1) => tob_data_bus,
        packet_merger_data(5) => (Others => '0'), -- correct version assembled in TOB_output_block
        packet_merger_valid(0) => '1',
        packet_merger_valid(4 downto 1) => tob_valid_bus,
        packet_merger_valid(5) => '1',
        packet_merger_last(0) => '1',
        packet_merger_last(4 downto 1) => tob_last_bus,
        packet_merger_last(5) => '1',
        packet_merger_ready(0) => dummy_sig(0),
        packet_merger_ready(4 downto 1) => tob_ready_bus,
        packet_merger_ready(5) => dummy_sig(1),
        packet_data         => tob_packet_data_sig,
        packet_valid        => tob_packet_valid_sig,
        packet_last         => tob_packet_last_sig,
        packet_sub_last     => tob_packet_sub_last_sig,
        packet_ready        => '1'
    );
 
TOB_Header_block: process(clk)
variable header: std_logic_vector(63 downto 0) := (Others => '0');
begin
    if rising_edge(clk) then
        if (ttc_read_sig = '1') then
            ttc_valid_bus <= fpga_tob_enabled; -- only trigger each FPGA if it is enabled...
        else
            ttc_valid_bus <= (Others => '0');
        end if;
        if (ttc_valid_sig = '1') then
            header := ttc_dout(43 downto 12) & DATA_FORMAT_VERSION & "0" & x"00" & ttc_dout(11 downto 0) & x"01"; -- Phase-I header
            L1A_seen <= '1';
            Last_L1ID_merged <= ttc_dout(43 downto 12);
        else
            L1A_seen <= '0';
        end if;
        tob_header_data_sig <= header
        -- pragma translate_off
        after 2 ns
        -- pragma translate_on
        ;
    end if;
end process TOB_Header_block;
 
-- Suppress embedded trailers in the merged TOB packet and propagate errors to the final trailer
TOB_output_block: process(clk)
variable trailer: std_logic_vector(63 downto 0);
begin
    if rising_edge(clk) then
        if (tob_merger_start_sig = '1') then
            trailer := x"0000000" & "00" & error_bus(5 downto 4) & x"00" & error_bus(3 downto 0) & eFEX_number & x"000";
        end if;
        if (tob_packet_source_sig /= "000") and (tob_packet_source_sig /= "101") and (tob_packet_sub_last_sig = '1') then
            trailer(36 downto 32) := trailer(36 downto 32) or tob_packet_data_sig(36 downto 32); -- Control Error and Status Map
            trailer(31 downto 24) := tob_packet_data_sig(31 downto 24); -- TSN and NSlice
            trailer(23 downto 20) := trailer(23 downto 20) or tob_packet_data_sig(23 downto 20); -- Processor Error Map
            merged_fifo_valid_sig(0) <= '0';
        else
            merged_fifo_valid_sig(0) <= tob_packet_valid_sig;
        end if;
        if (tob_packet_last_sig = '1') then
            merged_fifo_data_sig(0) <= trailer;
        else
            merged_fifo_data_sig(0) <= tob_packet_data_sig;
        end if;
        merged_fifo_last_sig(0) <= tob_packet_last_sig;
    end if;
end process TOB_output_block;
 
TOB_packet_merged_block: process(clk)
begin
    if rising_edge(clk) then
        for i in 0 to 3 loop
            if (tob_valid_bus(i) = '1') and (tob_last_bus(i) = '1') and (tob_ready_bus(i) = '1') then
                TOB_packet_merged_bus(i) <= '1';
            else
                TOB_packet_merged_bus(i) <= '0';
            end if;
        end loop;
    end if;
end process TOB_packet_merged_block;
 
TOB_enable_error_block: process(clk)
variable tob_good: std_logic_vector(3 downto 0);
variable error: std_logic_vector(5 downto 0);
begin
    if rising_edge(clk) then
        if rst_clk = '1' then
            tob_good := (Others => '0');
            error := (Others => '0');
        else
            if (state_sig = idle) then
                tob_good := (Others => '0');
                error := (Others => '0');
            elsif (state_sig = prepare_tobs) then
                for i in 0 to 3 loop
                    if (tob_packet_to_merge_bus(i) = '1') then
                        tob_good(i) := '1';
                    end if;
                    if (packet_missing_bus(i) = '1') then
                        error(i) := '1';
                        error(4) := '1';
                    end if;
                    if (packet_created_bus(i) = '1') then
                        error(i) := '1';
                        error(5) := '1';
                    end if;
                end loop;
            end if;
        end if;
        tob_good_bus <= tob_good
        -- pragma translate_off
        after 2 ns
        -- pragma translate_on
        ;
        error_bus <= error
        -- pragma translate_off
        after 2 ns
        -- pragma translate_on
        ;
    end if;
end process TOB_enable_error_block;
 
-- MUX any debug packets into the merged debug stream
Debug_MUX : efex_packet_mux
    GENERIC MAP (
        NSRC => 4
    )
    PORT MAP (
        clk                 => clk,
        rst_clk             => rst_clk,
        eFEX_number         => eFEX_number,
        pause               => '0',
        packet_mux_enabled  => fpga_tob_enabled,
        packet_mux_reset    => (Others => '0'),
        packet_mux_source   => OPEN,
        packet_mux_data     => debug_data_bus,
        packet_mux_valid    => debug_valid_bus,
        packet_mux_last     => debug_last_bus,
        packet_mux_ready    => debug_ready_bus,
        packet_data         => merged_fifo_data_sig(1),
        packet_valid        => debug_fifo_valid_sig,
        packet_last         => debug_fifo_last_sig,
        packet_ready        => '1'
    );
 
merged_fifo_valid_sig(1) <= debug_fifo_valid_sig and debug_enable_sig;
merged_fifo_last_sig(1) <= debug_fifo_last_sig;
 
Output_register_block: process(clk)
begin
    if rising_edge(clk) then
        merged_fifo_data <= merged_fifo_data_sig;
        merged_fifo_valid <= merged_fifo_valid_sig;
        merged_fifo_last <= merged_fifo_last_sig;
    end if;
end process Output_register_block;
 
-- Drop debug packets whilst debug pause is asserted, switching state during idle after end of packet
Debug_enable_block: process(clk)
variable debug_enable, packet_active: std_logic;
begin
    if rising_edge(clk) then
        if (rst_clk = '1') then
            debug_enable := '1';
            packet_active := '0';
        else
            if (debug_fifo_valid_sig = '1') then
                if (debug_fifo_last_sig = '1') then
                    packet_active := '0';
                else
                    packet_active := '1';
                end if;
            end if;
            if (packet_active = '0') then
                if (pause(1) = '1') then
                    debug_enable := '0';
                else
                    debug_enable := '1';
                end if;
            end if;
        end if;
        debug_enable_sig <= debug_enable
-- pragma translate_off
        after 2 ns
-- pragma translate_on
        ;
    end if;
end process Debug_enable_block;
 
pulse_block: process(clk)
variable ttc_read, tob_merger_start: std_logic;
begin
    if rising_edge(clk) then
        if (state_sig = start_event) then
            ttc_read := '1';
        else
            ttc_read := '0';
        end if;
        if (state_sig = start_merger) then
            tob_merger_start := '1';
        else
            tob_merger_start := '0';
        end if;
        ttc_read_sig <= ttc_read
        -- pragma translate_off
        after 2 ns
        -- pragma translate_on
        ;
        ttc_valid_sig <= ttc_read_sig
        -- pragma translate_off
        after 2 ns
        -- pragma translate_on
        ;
        tob_merger_start_sig <= tob_merger_start
        -- pragma translate_off
        after 2 ns
        -- pragma translate_on
        ;
    end if;
end process pulse_block;
 
ttc_rd_en <= ttc_read_sig;
 
SRLC32E_fifo_delay : SRLC32E
    generic map (INIT => X"00000000")
    port map (
    Q   => Open,
    Q31 => fifo_delay_end,          -- SRL cascaded data output
    A   => (Others => '1'),         -- Delay input
    CE  => '1',                     -- Clock enable input
    CLK => clk,                     -- Clock input
    D   => fifo_delay_start         -- SRL data input
    );
 
ifg_delay_strobe : for i in 0 to DELAY_DEPTH - 2 generate
    SRLC32E_delay_strobe : SRLC32E
        generic map (
            INIT => X"00000000")
        port map (
            Q   => Open,
            Q31 => q_i(i+1),                -- SRL cascaded data output
            A   => (Others => '1'),         -- Select input
            CE  => '1',                     -- Clock enable input
            CLK => clk,                   -- Clock input
            D   => q_i(i)                   -- SRL data input
            );
    end generate ifg_delay_strobe;
 
q_i(0) <= ifg_delay_start;
 
actual_ifg_delay_block: process(clk)
variable input_delay: integer range 0 to 15;
begin
    if rising_edge(clk) then
        input_delay := to_integer(unsigned(ifg_duration));
        if (input_delay > DELAY_DEPTH) then
            input_delay := DELAY_DEPTH;
        end if;
        ifg_delay_end <= q_i(input_delay);
    end if;
end process actual_ifg_delay_block;
 
state_machine: process(clk)
variable next_state: STATE_TYPE := idle;
variable processor_ready: std_logic_vector(3 downto 0);
variable fifo_delay: unsigned(2 downto 0);
variable fifo_start, ifg_start: std_logic;
begin
    if rising_edge(clk) then
        fifo_start := '0';
        ifg_start := '0';
        if rst_clk = '1' then
            next_state := idle;
            fifo_delay := (Others => '1');
        else
            case state_sig is
                when wait_fifos =>
                    if (input_fifo_empty = x"0") then
                        next_state := start_event;
                    elsif (fifo_delay_end = '1') then
                        next_state := idle;
                    else
                        next_state := wait_fifos;
                    end if;
                when start_event =>
                    next_state := prepare_tobs;
-- Increment FIFO delay credit
                    if (fifo_delay < 7) then
                        fifo_delay := fifo_delay + 1;
                    end if;
                when prepare_tobs =>
                    for i in 0 to 3 loop
                        if (tob_packet_ready_bus(i) = '1') then
                            processor_ready(i) := '1';
                        end if;
                    end loop;
                    if (processor_ready = fpga_tob_enabled) then
                        next_state := start_merger;
                    else
                        next_state := prepare_tobs;
                    end if;
                when start_merger =>
                    next_state := merge_tobs;
                when merge_tobs =>
                    if (tob_packet_last_sig = '1') then
                        next_state := ifg;
                        ifg_start := '1';
                    else
                        next_state := merge_tobs;
                    end if;
                when ifg =>
                    if (ifg_delay_end = '1') then
                        next_state := idle;
                    else
                        next_state := ifg;
                    end if;
                when others =>  -- idle
                    processor_ready := (Others => '0');
                    if (ttc_fifo_empty = '0') and (pause(0) = '0') then
-- TOB FIFOs all have an event waiting or we have no FIFO delay credit left
                        if (input_fifo_empty = x"0") or (fifo_delay = "000") then
                            next_state := start_event;
                        else
                            next_state := wait_fifos;
                            fifo_start := '1';
                            fifo_delay := fifo_delay - 1;
                        end if;
                    else
                        next_state := idle;
                    end if;
            end case;
        end if;
        state_sig <= next_state
        -- pragma translate_off
        after 2 ns
        -- pragma translate_on
        ;
        fifo_delay_start <= fifo_start
        -- pragma translate_off
        after 2 ns
        -- pragma translate_on
        ;
        ifg_delay_start <= ifg_start
        -- pragma translate_off
        after 2 ns
        -- pragma translate_on
        ;
    end if;
end process state_machine;
 
end rtl;