rtl Architecture Reference

Processes
TOB_Header_block	( clk )
TOB_output_block	( clk )
TOB_packet_merged_block	( clk )
TOB_enable_error_block	( clk )
Output_register_block	( clk )
Debug_enable_block	( clk )
pulse_block	( clk )
actual_ifg_delay_block	( clk )
state_machine	( clk )

Components
efex_tob_processer	<Entity efex_tob_processer>
efex_packet_merger	<Entity efex_packet_merger>
	Input signals.
efex_packet_mux	<Entity efex_packet_mux>
	FIFO signals.
SRLC32E
	FIFO signals.

Types
STATE_TYPE	( idle , wait_fifos , start_event , prepare_tobs , start_merger , merge_tobs , ifg )

Signals
state_sig	STATE_TYPE
debug_data_bus	packet_data_array ( 3 downto 0 )
tob_data_bus	packet_data_array ( 3 downto 0 )
debug_valid_bus	std_logic_vector ( 3 downto 0 )
debug_last_bus	std_logic_vector ( 3 downto 0 )
debug_ready_bus	std_logic_vector ( 3 downto 0 )
tob_valid_bus	std_logic_vector ( 3 downto 0 )
tob_last_bus	std_logic_vector ( 3 downto 0 )
tob_ready_bus	std_logic_vector ( 3 downto 0 )
ttc_valid_bus	std_logic_vector ( 3 downto 0 )
tob_packet_ready_bus	std_logic_vector ( 3 downto 0 )
tob_packet_to_merge_bus	std_logic_vector ( 3 downto 0 )
tob_good_bus	std_logic_vector ( 3 downto 0 )
packet_missing_bus	std_logic_vector ( 3 downto 0 )
packet_created_bus	std_logic_vector ( 3 downto 0 )
tob_packet_data_sig	std_logic_vector ( 63 downto 0 )
tob_header_data_sig	std_logic_vector ( 63 downto 0 )
ttc_read_sig	std_logic
ttc_valid_sig	std_logic
tob_packet_valid_sig	std_logic
tob_packet_last_sig	std_logic
tob_packet_sub_last_sig	std_logic
tob_merger_start_sig	std_logic
debug_enable_sig	std_logic
debug_fifo_valid_sig	std_logic
debug_fifo_last_sig	std_logic
fifo_delay_start	std_logic
fifo_delay_end	std_logic
ifg_delay_start	std_logic
ifg_delay_end	std_logic
q_i	std_logic_vector ( DELAY_DEPTH- 1 downto 0 )
tob_packet_source_sig	std_logic_vector ( 2 downto 0 )
dummy_sig	std_logic_vector ( 1 downto 0 )
error_bus	std_logic_vector ( 5 downto 0 )
merged_fifo_data_sig	packet_data_array ( 1 downto 0 )
merged_fifo_valid_sig	std_logic_vector ( 1 downto 0 )
merged_fifo_last_sig	std_logic_vector ( 1 downto 0 )

Instantiations
tob_processer	efex_tob_processer <Entity efex_tob_processer>
tob_merger	efex_packet_merger <Entity efex_packet_merger>
debug_mux	efex_packet_mux <Entity efex_packet_mux>
srlc32e_fifo_delay	srlc32e
srlc32e_delay_strobe	srlc32e

Detailed Description

Definition at line 50 of file efex_tob_merger.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/efex_tob_merger.vhd