efex_tob_merger Entity Reference

Inheritance diagram for efex_tob_merger:

Entities
rtl	architecture

Libraries
ieee
infrastructure_lib

Use Clauses
std_logic_1164
numeric_std
packet_mux_type	Package <packet_mux_type>

Generics
DATA_FORMAT_VERSION	std_logic_vector ( 2 DOWNTO 0 ) := " 001 "
DELAY_DEPTH	Integer range 0 to 15 := 15

Ports
clk	in	std_logic
rst_clk	in	std_logic
eFEX_number	in	std_logic_vector ( 7 downto 0 )
ifg_duration	in	std_logic_vector ( 3 downto 0 )
fpga_tob_enabled	in	std_logic_vector ( 3 downto 0 )
pause	in	std_logic_vector ( 1 downto 0 )
ttc_rd_en	out	STD_LOGIC
ttc_dout	in	std_logic_vector ( 49 DOWNTO 0 )
ttc_fifo_empty	in	STD_LOGIC
input_fifo_empty	in	std_logic_vector ( 3 downto 0 )
fpga_tob_data	in	packet_data_array ( 3 downto 0 )
fpga_tob_valid	in	std_logic_vector ( 3 downto 0 )
fpga_tob_last	in	std_logic_vector ( 3 downto 0 )
fpga_tob_ready	out	std_logic_vector ( 3 downto 0 )
merged_fifo_data	out	packet_data_array ( 1 downto 0 )
merged_fifo_valid	out	std_logic_vector ( 1 downto 0 )
merged_fifo_last	out	std_logic_vector ( 1 downto 0 )
L1A_seen	out	STD_LOGIC
Last_L1ID_merged	out	std_logic_vector ( 31 downto 0 )
TOB_packet_merged_bus	out	std_logic_vector ( 3 downto 0 )
TOB_packet_missing_bus	out	std_logic_vector ( 3 downto 0 )
debug_packet_created_bus	out	std_logic_vector ( 3 downto 0 )

Detailed Description

Definition at line 13 of file efex_tob_merger.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/efex_tob_merger.vhd