efex_packet_mux Entity Reference

AXI-stream MUX into packet engine... More...

Inheritance diagram for efex_packet_mux:

Entities
rtl	architecture
	AXI-stream MUX into packet engine... More...

Libraries
ieee
infrastructure_lib

Use Clauses
std_logic_1164
numeric_std
packet_mux_type	Package <packet_mux_type>

Generics
NSRC	positive := 4

Ports
clk	in	std_logic
rst_clk	in	std_logic
eFEX_number	in	std_logic_vector ( 7 downto 0 )
pause	in	std_logic := ' 0 '
packet_mux_enabled	in	std_logic_vector ( NSRC- 1 downto 0 )
packet_mux_reset	in	std_logic_vector ( NSRC- 1 downto 0 )
packet_mux_source	out	std_logic_vector ( 3 downto 0 )
packet_mux_data	in	packet_data_array ( NSRC- 1 downto 0 )
		Input signals.
packet_mux_valid	in	std_logic_vector ( NSRC- 1 downto 0 )
packet_mux_last	in	std_logic_vector ( NSRC- 1 downto 0 )
packet_mux_ready	out	std_logic_vector ( NSRC- 1 downto 0 )
packet_data	out	std_logic_vector ( 63 DOWNTO 0 )
		FIFO signals.
packet_valid	out	std_logic
packet_last	out	std_logic
packet_ready	in	std_logic

Detailed Description

AXI-stream MUX into packet engine...

Monitors each input to feed next en route to Aurora

Simple round-robin polling with a fallback switch to zero during hunting if packet available (very crude priority to TOB packet!) Protection against input being reset whilst active...

Heavily based on IPBus mac_arbiter: "Arbitrates access by several packet sources to a single MAC core

Dave Newbold, March 2011"

Author

David Sankey

Definition at line 23 of file efex_packet_mux.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/efex_packet_mux.vhd