rtl Architecture Reference

AXI-stream MUX into packet engine... More...

Processes
PROCESS_42	( clk )

Types
STATE_TYPE	( running , starting , hunting )

Signals
state_sig	STATE_TYPE := hunting
src	unsigned ( 3 downto 0 ) := ( others = > ' 0 ' )
hunting_src	unsigned ( 3 downto 0 ) := ( others = > ' 0 ' )
sel	integer range 0 to NSRC+ 1 := 0
hunting_sel	integer range 0 to NSRC+ 1 := 0
active	std_logic
packet_mux_data_sig	packet_data_array ( NSRC+ 1 downto 0 )
packet_mux_valid_sig	std_logic_vector ( NSRC+ 1 downto 0 )
packet_mux_last_sig	std_logic_vector ( NSRC+ 1 downto 0 )
packet_mux_reset_sig	std_logic_vector ( NSRC+ 1 downto 0 )
packet_mux_ready_sig	std_logic_vector ( NSRC- 1 downto 0 )
packet_mux_enabled_sig	std_logic_vector ( NSRC- 1 downto 0 )

Detailed Description

AXI-stream MUX into packet engine...

Monitors each input to feed next en route to Aurora

Simple round-robin polling with a fallback switch to zero during hunting if packet available (very crude priority to TOB packet!) Protection against input being reset whilst active...

Heavily based on IPBus mac_arbiter: "Arbitrates access by several packet sources to a single MAC core

Dave Newbold, March 2011"

Author

David Sankey

Definition at line 48 of file efex_packet_mux.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/efex_packet_mux.vhd