ttc_fifo_block Entity Reference

Switch TTC FIFO data to correct stream depending on destination_enable... More...

Inheritance diagram for ttc_fifo_block:

Entities
rtl	architecture
	Switch TTC FIFO data to correct stream depending on destination_enable... More...

Libraries
ieee
	Use standard library.

Use Clauses
std_logic_1164
numeric_std

Generics
DELAY_DEPTH	Integer range 0 to 255 := 3

Ports
clk40	in	std_logic
clk_320	in	std_logic
rst_ttc	in	std_logic
ttc_wr_en	in	std_logic
ttc_rd_en	in	std_logic
ttc_din	in	std_logic_vector ( 49 DOWNTO 0 )
ttc_rd_en_A	in	std_logic
ttc_empty_A	out	std_logic
ttc_dout_A	out	std_logic_vector ( 49 DOWNTO 0 )
ttc_rd_en_B	in	std_logic
ttc_empty_B	out	std_logic
ttc_dout_B	out	std_logic_vector ( 49 DOWNTO 0 )
destination_enable	in	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
readout_delay	in	std_logic_vector ( 7 downto 0 )

Detailed Description

Switch TTC FIFO data to correct stream depending on destination_enable...

Buffer input and switch TTC FIFO data to correct stream depending on destination_enable and L1ID With both streams active odd events go to stream A, even to stream B With only one stream active all events go to that stream

Author

David Sankey

Definition at line 15 of file ttc_fifo_block.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd