ttc_fifo_block.vhd

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
ENTITY ttc_fifo_block IS
    generic(
        DELAY_DEPTH     : Integer range 0 to 255 := 3 -- Number of SRLC32E to cascade for delayed L1A strobe over and above ftm_ttc_mode delay
    );
    PORT (
-- clocks etc
        clk40           : in std_logic;
        clk_320         : in std_logic;
-- TTC input FIFO
        rst_ttc         : in std_logic;
        ttc_wr_en       : in std_logic;
        ttc_rd_en       : in std_logic;
        ttc_din         : in std_logic_vector(49 DOWNTO 0);
-- TTC output FIFOs
        ttc_rd_en_A     : in std_logic;
        ttc_empty_A     : out std_logic;
        ttc_dout_A      : out std_logic_vector(49 DOWNTO 0);
        ttc_rd_en_B     : in std_logic;
        ttc_empty_B     : out std_logic;
        ttc_dout_B      : out std_logic_vector(49 DOWNTO 0);
-- input and output control
        destination_enable  : in std_logic_vector(1 downto 0) := (Others => '0');
        readout_delay   : in std_logic_vector(7 downto 0)
    );
END ENTITY ttc_fifo_block;
 
Architecture rtl of ttc_fifo_block is
 
COMPONENT SRLC32E is
    generic(
        INIT     : std_logic_vector(31 downto 0) := (Others => '0')
    );
    port(
        CLK : in std_logic;
        D : in std_logic;
        CE : in std_logic;
        A : in std_logic_vector(4 downto 0);
        Q : out std_logic;
        Q31 : out std_logic
    );
end COMPONENT SRLC32E;
 
COMPONENT fifo_40M_160M is
    PORT (
        rst : IN STD_LOGIC;
        wr_clk : IN STD_LOGIC;
        rd_clk : IN STD_LOGIC;
        din : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
        wr_en : IN STD_LOGIC;
        rd_en : IN STD_LOGIC;
        dout : OUT STD_LOGIC_VECTOR(49 DOWNTO 0);
        full : OUT STD_LOGIC;
        empty : OUT STD_LOGIC
    );
END COMPONENT fifo_40M_160M;
 
    signal ttc_delay_d: std_logic_vector(49 DOWNTO 0);
    signal ttc_delay_q: std_logic_vector(49 DOWNTO 0);
    signal ttc_fifo_rd, ttc_fifo_wr, ttc_fifo_wait: std_logic;
    signal ttc_delay_wr_A, ttc_delay_wr_B: std_logic;
    signal ttc_fifo_rd_A, ttc_fifo_rd_B: std_logic;
    signal ttc_fifo_empty_A, ttc_fifo_empty_B: std_logic;
    signal ttc_veto_clk40, ttc_veto_clk320: std_logic := '1';
    signal q_i: std_logic_vector(DELAY_DEPTH DOWNTO 0);
    signal actual_delay: integer range 0 to 255;
 
BEGIN
 
-- TTC offset in SRL32 is bottom byte of readout_delay...
actual_delay_block: process(clk_320)
variable input_delay: integer range 0 to 255;
begin
    if rising_edge(clk_320) then
        input_delay := to_integer(unsigned(readout_delay));
        if (input_delay > DELAY_DEPTH) then
            input_delay := DELAY_DEPTH;
        end if;
        actual_delay <= input_delay;
    end if;
end process actual_delay_block;
 
-- generate a stretched 40 MHz veto out of the original 'reset' signal
ttc_veto_block_clk40 : process(clk40)
    Variable stretch: std_logic_vector(15 downto 0) := (Others => '1');
    begin
      if rising_edge(clk40) then
        if (rst_ttc /= '0') then
          stretch := (Others => '1');
          ttc_veto_clk40 <= '1';
        else
          stretch := stretch(14 downto 0) & "0";
          ttc_veto_clk40 <= stretch(15);
        end if;
      end if;
    end process ttc_veto_block_clk40;
 
-- generate a 320 MHz veto out of the clk40 signals
ttc_veto_block_clk320 : process(clk_320)
    begin
      if rising_edge(clk_320) then
        if (rst_ttc /= '0') or (ttc_veto_clk40 /= '0') then
          ttc_veto_clk320 <= '1';
        else
          ttc_veto_clk320 <= '0';
        end if;
      end if;
    end process ttc_veto_block_clk320;
 
q_i(0) <= ttc_rd_en when ttc_veto_clk40 = '0' else '0';
ttc_fifo_wr <= ttc_wr_en when ttc_veto_clk40 = '0' else '0';
ttc_fifo_rd_A <= ttc_rd_en_A when ttc_veto_clk320 = '0' else '0';
ttc_fifo_rd_B <= ttc_rd_en_B when ttc_veto_clk320 = '0' else '0';
ttc_empty_A <= ttc_fifo_empty_A when ttc_veto_clk320 = '0' else '1';
ttc_empty_B <= ttc_fifo_empty_B when ttc_veto_clk320 = '0' else '1';
 
ttc_delay_strobe : for i in 0 to DELAY_DEPTH - 1 generate
    SRLC32E_delay_strobe : SRLC32E
        generic map (
            INIT => X"00000000")
        port map (
            Q   => Open,
            Q31 => q_i(i+1),                -- SRL cascaded data output
            A   => (Others => '1'),         -- Select input
            CE  => '1',                     -- Clock enable input
            CLK => CLK40,                   -- Clock input
            D   => q_i(i)                   -- SRL data input
            );
    end generate ttc_delay_strobe;
 
ttc_fifo_delay: fifo_40M_160M
    port map (
        rst     => rst_ttc,
        wr_clk  => clk40,
        rd_clk  => clk40,
        din     => ttc_din,
        wr_en   => ttc_fifo_wr,
        rd_en   => ttc_fifo_rd,
        dout    => ttc_delay_q,
        full    => OPEN,
        empty   => Open
    );
 
ttc_fifo_A: fifo_40M_160M
    port map (
        rst     => rst_ttc,
        wr_clk  => clk40,
        rd_clk  => clk_320,
        din     => ttc_delay_d,
        wr_en   => ttc_delay_wr_A,
        rd_en   => ttc_fifo_rd_A,
        dout    => ttc_dout_A,
        full    => OPEN,
        empty   => ttc_fifo_empty_A
    );
 
ttc_fifo_B: fifo_40M_160M
    port map (
        rst     => rst_ttc,
        wr_clk  => clk40,
        rd_clk  => clk_320,
        din     => ttc_delay_d,
        wr_en   => ttc_delay_wr_B,
        rd_en   => ttc_fifo_rd_B,
        dout    => ttc_dout_B,
        full    => OPEN,
        empty   => ttc_fifo_empty_B
    );
 
ttc_fifo_connect: process(clk40)
    Begin
        if rising_edge(clk40) then
            ttc_fifo_rd <= q_i(actual_delay) and not ttc_veto_clk40
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            ttc_fifo_wait <= ttc_fifo_rd and not ttc_veto_clk40
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            ttc_delay_d <= ttc_delay_q
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            case destination_enable is
            when "01" =>
                ttc_delay_wr_A <= ttc_fifo_wait and not ttc_veto_clk40
-- pragma translate_off
                after 2 ns
-- pragma translate_on
                ;
                ttc_delay_wr_B <= '0'
-- pragma translate_off
                after 2 ns
-- pragma translate_on
                ;
            when "10" =>
                ttc_delay_wr_A <= '0'
-- pragma translate_off
                after 2 ns
-- pragma translate_on
                ;
                ttc_delay_wr_B <= ttc_fifo_wait and not ttc_veto_clk40
-- pragma translate_off
                after 2 ns
-- pragma translate_on
                ;
-- Odd events to A, even to B
            when "11" =>
                ttc_delay_wr_A <= ttc_fifo_wait and ttc_delay_q(12) and not ttc_veto_clk40
-- pragma translate_off
                after 2 ns
-- pragma translate_on
                ;
                ttc_delay_wr_B <= ttc_fifo_wait and not ttc_delay_q(12) and not ttc_veto_clk40
-- pragma translate_off
                after 2 ns
-- pragma translate_on
                ;
            when Others =>
                ttc_delay_wr_A <= '0'
-- pragma translate_off
                after 2 ns
-- pragma translate_on
                ;
                ttc_delay_wr_B <= '0'
-- pragma translate_off
                after 2 ns
-- pragma translate_on
                ;
            end case;
        end if;
    End process ttc_fifo_connect;
 
END Architecture rtl;