rtl Architecture Reference

Switch TTC FIFO data to correct stream depending on destination_enable... More...

Processes
actual_delay_block	( clk_320 )
ttc_veto_block_clk40	( clk40 )
ttc_veto_block_clk320	( clk_320 )
ttc_fifo_connect	( clk40 )

Components
SRLC32E
fifo_40M_160M

Signals
ttc_delay_d	std_logic_vector ( 49 DOWNTO 0 )
ttc_delay_q	std_logic_vector ( 49 DOWNTO 0 )
ttc_fifo_rd	std_logic
ttc_fifo_wr	std_logic
ttc_fifo_wait	std_logic
ttc_delay_wr_A	std_logic
ttc_delay_wr_B	std_logic
ttc_fifo_rd_A	std_logic
ttc_fifo_rd_B	std_logic
ttc_fifo_empty_A	std_logic
ttc_fifo_empty_B	std_logic
ttc_veto_clk40	std_logic := ' 1 '
ttc_veto_clk320	std_logic := ' 1 '
q_i	std_logic_vector ( DELAY_DEPTH DOWNTO 0 )
actual_delay	integer range 0 to 255

Instantiations
srlc32e_delay_strobe	srlc32e
ttc_fifo_delay	fifo_40m_160m
ttc_fifo_a	fifo_40m_160m
ttc_fifo_b	fifo_40m_160m

Detailed Description

Switch TTC FIFO data to correct stream depending on destination_enable...

Buffer input and switch TTC FIFO data to correct stream depending on destination_enable and L1ID With both streams active odd events go to stream A, even to stream B With only one stream active all events go to that stream

Author

David Sankey

Definition at line 42 of file ttc_fifo_block.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd