efex_packet_builder Entity Reference

AXI-stream version of packet engine... More...

Inheritance diagram for efex_packet_builder:

Entities
universal	architecture
	AXI-stream version of packet engine... More...

Libraries
ieee
	Use standard library.

Use Clauses
std_logic_1164
numeric_std

Ports
clk	in	std_logic
rst_clk	in	std_logic
packet_data	in	std_logic_vector ( 63 DOWNTO 0 )
		FIFO signals.
packet_valid	in	std_logic
packet_last	in	std_logic
packet_ready	out	std_logic
payload_data	out	std_logic_vector ( 63 DOWNTO 0 )
		towards Aurora readout
payload_valid	out	std_logic
payload_last	out	std_logic
tready_data	in	std_logic

Detailed Description

AXI-stream version of packet engine...

Takes an incoming packet and calculates Header and Payload CRC en route to Aurora

Author

David Sankey

Definition at line 13 of file efex_packet_builder.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/efex_packet_builder.vhd