universal Architecture Reference

AXI-stream version of packet engine... More...

Processes
buffer_input	( clk )
build_crc_word	( clk )
send_data	( clk )
state_machine	( clk )

Components
CRC20	<Entity CRC20>

Types
STATE_TYPE	( idle , capture_l1id , do_hdr_crc , wait_hdr_crc , send_l1id , send_payload , build_trailer , do_trailer_crc , wait_trailer_crc , send_trailer , wait_end )

Signals
valid_sig	std_logic
last_sig	std_logic
ready_sig	std_logic
force_ready_sig	std_logic
input_active_sig	std_logic
do_crc9	std_logic
calc_crc20	std_logic
reset_crc20	std_logic
send_crc9	std_logic
send_crc20	std_logic
input_valid_sig	std_logic
input_data_end_sig	std_logic
prefetch_sig	std_logic
data_sig	std_logic_vector ( 63 DOWNTO 0 )
inputdata_sig	std_logic_vector ( 63 DOWNTO 0 )
crc_word	std_logic_vector ( 63 DOWNTO 0 )
crc9val	std_logic_vector ( 8 DOWNTO 0 )
crc20val	std_logic_vector ( 19 DOWNTO 0 )
state_sig	STATE_TYPE

Instantiations
crc9_block	CRC20 <Entity CRC20>
crc20_block	CRC20 <Entity CRC20>

Detailed Description

AXI-stream version of packet engine...

Takes an incoming packet and calculates Header and Payload CRC en route to Aurora

Author

David Sankey

Definition at line 31 of file efex_packet_builder.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/efex_packet_builder.vhd