packet_fifo_reset_block.vhd

Go to the documentation of this file.

 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
ENTITY packet_fifo_reset_block IS
    PORT (
        clk         : in std_logic;
        rst         : in std_logic;
        fifo_valid  : in std_logic;
        fifo_last   : in std_logic;
        fifo_error  : in std_logic;
        fifo_reset  : out std_logic
    );
END ENTITY packet_fifo_reset_block;
 
Architecture rtl of packet_fifo_reset_block is
 
signal fifo_reset_sig: std_logic;
 
BEGIN
 
    fifo_reset <= fifo_reset_sig;
 
    fifo_reset_block: process(clk)
-- stretched reset signal
        Variable stretch: std_logic_vector(7 downto 0) := (Others => '1');
-- armed set means we are sensitive to incoming data to continue reset
        Variable armed : std_logic := '0';
        begin
            if rising_edge(clk) then
-- Reset on incoming rst but don't enable check on incoming data...
                if (rst = '1') then
                    stretch := (Others => '1');
                    armed := '0';
-- Reset on error from FIFO and arm stretch for incoming data
                elsif (fifo_error = '1') then
                    stretch := (Others => '1');
                    armed := '1';
-- Clear reset if tlast seen on input
                elsif (fifo_valid = '1') and (fifo_last = '1') and (armed = '1') then
                    stretch := (Others => '0');
-- Otherwise extend reset if still incoming data...
                elsif (fifo_valid = '1') and (armed = '1') then
                    stretch := (Others => '1');
                else
                    stretch := stretch(6 downto 0) & "0";
                end if;
-- Finally make sure that armed is cleared at end of reset...
                if (fifo_reset_sig = '0') then
                    armed := '0';
                end if;
                fifo_reset_sig <= stretch(7)
    -- pragma translate_off
                after 2 ns
    -- pragma translate_on
                ;
            end if;
        end process fifo_reset_block;
 
END Architecture rtl;