fifo_selector.vhd

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
ENTITY fifo_selector IS
  port (
    clk_320             : in std_logic;
-- FIFO data from MGT block
    fifo_data           : in std_logic_vector (63 DOWNTO 0);
    fifo_valid          : in std_logic;
    fifo_last           : in std_logic;
-- data to FIFO A
    fifo_data_A         : out std_logic_vector (63 DOWNTO 0);
    fifo_valid_A        : out std_logic;
    fifo_last_A         : out std_logic;
-- data to FIFO B
    fifo_data_B         : out std_logic_vector (63 DOWNTO 0);
    fifo_valid_B        : out std_logic;
    fifo_last_B         : out std_logic;
-- switch control
    destination_enable  : in std_logic_vector(1 downto 0) := (Others => '0')
  );
END ENTITY fifo_selector;
 
Architecture rtl of fifo_selector is
 
   Signal destination_selected: std_logic_vector(1 downto 0) := (Others => '0');
   Signal fifo_valid_buf, fifo_last_buf: std_logic;
   Signal fifo_data_buf: std_logic_vector (63 DOWNTO 0);
 
Begin
 
buffer_block: process(clk_320)
    Begin
        if rising_edge(clk_320) then
            fifo_valid_buf <= fifo_valid
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            fifo_last_buf <= fifo_last
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            fifo_data_buf <= fifo_data
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    End process buffer_block;
 
tob_fifo_select: process(clk_320)
    Variable active: std_logic := '0';
    Begin
        if rising_edge(clk_320) then
            if (fifo_valid_buf = '1') and (fifo_last_buf = '1') then
                active := '0';
            elsif (fifo_valid = '1') and (active = '0') then
                active := '1';
                if (destination_enable = "11") then
-- Ping pong!
                    destination_selected <= (not fifo_data(32)) & fifo_data(32)
-- pragma translate_off
                    after 2 ns
-- pragma translate_on
                    ;
                else
                    destination_selected <= destination_enable
-- pragma translate_off
                    after 2 ns
-- pragma translate_on
                    ;
                end if;
            elsif (active = '0') then
                destination_selected <= (Others => '0')
-- pragma translate_off
                after 2 ns
-- pragma translate_on
                ;
            end if;
        end if;
    End process tob_fifo_select;
 
transmit_block : process(clk_320)
    Begin
        if rising_edge(clk_320) then
            fifo_data_A <= fifo_data_buf
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            fifo_data_B <= fifo_data_buf
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            fifo_valid_A <= fifo_valid_buf and destination_selected(0)
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            fifo_valid_B <= fifo_valid_buf and destination_selected(1)
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            fifo_last_A <= fifo_last_buf and destination_selected(0)
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            fifo_last_B <= fifo_last_buf and destination_selected(1)
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    End process transmit_block;
 
END Architecture rtl;