rtl Architecture Reference

Switch FIFO data to correct stream depending on destination_enable... More...

Processes
buffer_block	( clk_320 )
tob_fifo_select	( clk_320 )
transmit_block	( clk_320 )

Signals
destination_selected	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
fifo_valid_buf	std_logic
fifo_last_buf	std_logic
fifo_data_buf	std_logic_vector ( 63 DOWNTO 0 )

Detailed Description

Switch FIFO data to correct stream depending on destination_enable...

Buffer input and switch FIFO data to correct stream depending on destination_enable and L1ID With both streams active (TOB ping pong mode) odd events go to stream A, even to stream B With only one stream active all events go to that stream

Author

David Sankey

Definition at line 37 of file fifo_selector.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/fifo_selector.vhd