Instantiate the readout merging and routing logic... More...

Processes
MUX_monitor_block	( clk_320 )
bcr_clk40	( clk40 )
ecr_clk40	( clk40 )
bcr_tff_clk320	( clk_320 )
ecr_tff_clk320	( clk_320 )
bcr_clk320	( clk_320 )
ecr_clk320	( clk_320 )
Reset_block	( clk_320 )
L1A_enable_block	( clk_320 )
Enable_block	( clk_320 )

Constants
FPGA_mapping	STD_LOGIC_VECTOR ( 7 downto 0 ) := x " 9C "

Signals
rst_320_sig	std_logic
rst_320_end	std_logic
rst_320_delay	std_logic
l1a_enable_sig	std_logic
ipbus_tob_mgt_wbus_array	ipb_wbus_array ( 3 downto 0 )
ipbus_raw_mgt_wbus_array	ipb_wbus_array ( 3 downto 0 )
ipbus_tob_mgt_rbus_array	ipb_rbus_array ( 3 downto 0 )
ipbus_raw_mgt_rbus_array	ipb_rbus_array ( 3 downto 0 )
ipbus_merger_spy_wbus_array	ipb_wbus_array ( 1 downto 0 )
ipbus_built_fifo_wbus_array	ipb_wbus_array ( 1 downto 0 )
ipbus_merger_spy_rbus_array	ipb_rbus_array ( 1 downto 0 )
ipbus_built_fifo_rbus_array	ipb_rbus_array ( 1 downto 0 )
rst_ipbus_tob_mgt_addr_bus	std_logic_vector ( 3 downto 0 )
ipbus_tob_mgt_wraparound_bus	std_logic_vector ( 3 downto 0 )
rst_ipbus_raw_mgt_addr_bus	std_logic_vector ( 3 downto 0 )
ipbus_raw_mgt_wraparound_bus	std_logic_vector ( 3 downto 0 )
rst_ipbus_merger_spy_addr_bus	std_logic_vector ( 1 downto 0 )
ipbus_merger_spy_wraparound_bus	std_logic_vector ( 1 downto 0 )
rst_ipbus_built_fifo_addr_bus	std_logic_vector ( 1 downto 0 )
ipbus_built_fifo_wraparound_bus	std_logic_vector ( 1 downto 0 )
readout_delay	std_logic_vector ( 31 downto 0 )
tob_fifo_data_bus	packet_data_array ( 3 downto 0 )
tob_fifo_data_A_bus	packet_data_array ( 3 downto 0 )
tob_fifo_data_B_bus	packet_data_array ( 3 downto 0 )
tob_fifo_last_bus	std_logic_vector ( 3 downto 0 )
tob_fifo_last_A_bus	std_logic_vector ( 3 downto 0 )
tob_fifo_last_B_bus	std_logic_vector ( 3 downto 0 )
tob_fifo_valid_bus	std_logic_vector ( 3 downto 0 )
tob_fifo_valid_A_bus	std_logic_vector ( 3 downto 0 )
tob_fifo_valid_B_bus	std_logic_vector ( 3 downto 0 )
tob_packet_data_A_bus	packet_data_array ( 3 downto 0 )
tob_packet_data_B_bus	packet_data_array ( 3 downto 0 )
tob_packet_data_A_reg_bus	packet_data_array ( 3 downto 0 )
tob_packet_data_B_reg_bus	packet_data_array ( 3 downto 0 )
tob_packet_last_A_bus	std_logic_vector ( 3 downto 0 )
tob_packet_last_B_bus	std_logic_vector ( 3 downto 0 )
tob_packet_last_A_reg_bus	std_logic_vector ( 3 downto 0 )
tob_packet_last_B_reg_bus	std_logic_vector ( 3 downto 0 )
tob_packet_valid_A_bus	std_logic_vector ( 3 downto 0 )
tob_packet_valid_B_bus	std_logic_vector ( 3 downto 0 )
tob_packet_valid_A_reg_bus	std_logic_vector ( 3 downto 0 )
tob_packet_valid_B_reg_bus	std_logic_vector ( 3 downto 0 )
tob_packet_ready_A_bus	std_logic_vector ( 3 downto 0 )
tob_packet_ready_B_bus	std_logic_vector ( 3 downto 0 )
tob_packet_ready_A_reg_bus	std_logic_vector ( 3 downto 0 )
tob_packet_ready_B_reg_bus	std_logic_vector ( 3 downto 0 )
tob_fifo_reset_A_bus	std_logic_vector ( 3 downto 0 )
tob_fifo_reset_B_bus	std_logic_vector ( 3 downto 0 )
tob_fifo_fill_level_A_bus	fifo_status_array ( 3 downto 0 )
tob_fifo_fill_level_B_bus	fifo_status_array ( 3 downto 0 )
tob_packet_count_A_bus	fifo_status_array ( 3 downto 0 )
tob_packet_count_B_bus	fifo_status_array ( 3 downto 0 )
tob_fifo_empty_A_bus	std_logic_vector ( 3 downto 0 )
tob_fifo_empty_B_bus	std_logic_vector ( 3 downto 0 )
tob_input_error_A_bus	std_logic_vector ( 3 downto 0 )
tob_input_error_B_bus	std_logic_vector ( 3 downto 0 )
tob_fifo_error_A_bus	std_logic_vector ( 3 downto 0 )
tob_fifo_error_B_bus	std_logic_vector ( 3 downto 0 )
tob_mgt_packet_received_bus	std_logic_vector ( 3 downto 0 )
tob_mgt_safe_mode_bus	std_logic_vector ( 3 downto 0 )
tob_mgt_packet_err_bus	std_logic_vector ( 3 downto 0 )
tob_mgt_length_err_bus	std_logic_vector ( 3 downto 0 )
tob_mgt_bcn_err_bus	std_logic_vector ( 3 downto 0 )
tob_mgt_last_l1id_bus	mgt_data_array ( 3 downto 0 )
ttc_dout_A	std_logic_vector ( 49 DOWNTO 0 )
ttc_dout_B	std_logic_vector ( 49 DOWNTO 0 )
ttc_empty_A	std_logic
ttc_empty_B	std_logic
ttc_rd_en_A	std_logic
ttc_rd_en_B	std_logic
TOB_Block_A_pause	std_logic_vector ( 1 downto 0 )
TOB_Block_B_pause	std_logic_vector ( 1 downto 0 )
merged_fifo_data_A_bus	packet_data_array ( 1 downto 0 )
merged_fifo_data_B_bus	packet_data_array ( 1 downto 0 )
merged_fifo_last_A_bus	std_logic_vector ( 1 downto 0 )
merged_fifo_last_B_bus	std_logic_vector ( 1 downto 0 )
merged_fifo_valid_A_bus	std_logic_vector ( 1 downto 0 )
merged_fifo_valid_B_bus	std_logic_vector ( 1 downto 0 )
merged_fifo_fill_level_A_bus	fifo_status_array ( 1 downto 0 )
merged_fifo_fill_level_B_bus	fifo_status_array ( 1 downto 0 )
merged_packet_count_A_bus	fifo_status_array ( 1 downto 0 )
merged_packet_count_B_bus	fifo_status_array ( 1 downto 0 )
merged_input_error_A_bus	std_logic_vector ( 1 downto 0 )
merged_input_error_B_bus	std_logic_vector ( 1 downto 0 )
merged_fifo_error_A_bus	std_logic_vector ( 1 downto 0 )
merged_fifo_error_B_bus	std_logic_vector ( 1 downto 0 )
merged_fifo_reset_A_bus	std_logic_vector ( 1 downto 0 )
merged_fifo_reset_B_bus	std_logic_vector ( 1 downto 0 )
Last_L1ID_merger_A	std_logic_vector ( 31 downto 0 )
Last_L1ID_merger_B	std_logic_vector ( 31 downto 0 )
L1A_seen_bus	std_logic_vector ( 1 downto 0 )
TOB_packet_merged_A_bus	std_logic_vector ( 3 downto 0 )
TOB_packet_missing_A_bus	std_logic_vector ( 3 downto 0 )
debug_packet_created_A_bus	std_logic_vector ( 3 downto 0 )
TOB_packet_merged_B_bus	std_logic_vector ( 3 downto 0 )
TOB_packet_missing_B_bus	std_logic_vector ( 3 downto 0 )
debug_packet_created_B_bus	std_logic_vector ( 3 downto 0 )
raw_fifo_data_bus	packet_data_array ( 3 downto 0 )
raw_demux_data_bus	packet_data_array ( 3 downto 0 )
raw_fifo_data_A_bus	packet_data_array ( 3 downto 0 )
raw_fifo_data_B_bus	packet_data_array ( 3 downto 0 )
raw_demux_pause_bus	std_logic_vector ( 3 downto 0 )
raw_demux_pause_A_bus	std_logic_vector ( 3 downto 0 )
raw_demux_pause_B_bus	std_logic_vector ( 3 downto 0 )
raw_fifo_last_bus	std_logic_vector ( 3 downto 0 )
raw_demux_last_bus	std_logic_vector ( 3 downto 0 )
raw_fifo_last_A_bus	std_logic_vector ( 3 downto 0 )
raw_fifo_last_B_bus	std_logic_vector ( 3 downto 0 )
raw_fifo_valid_bus	std_logic_vector ( 3 downto 0 )
raw_demux_valid_bus	std_logic_vector ( 3 downto 0 )
raw_fifo_valid_A_bus	std_logic_vector ( 3 downto 0 )
raw_fifo_valid_B_bus	std_logic_vector ( 3 downto 0 )
raw_fifo_fill_level_bus	fifo_status_array ( 3 downto 0 )
raw_packet_count_bus	fifo_status_array ( 3 downto 0 )
raw_fifo_error_bus	std_logic_vector ( 3 downto 0 )
raw_input_error_bus	std_logic_vector ( 3 downto 0 )
raw_ram_fifo_error_bus	std_logic_vector ( 3 downto 0 )
raw_fifo_error_A_bus	std_logic_vector ( 3 downto 0 )
raw_fifo_error_B_bus	std_logic_vector ( 3 downto 0 )
raw_fifo_reset_bus	std_logic_vector ( 3 downto 0 )
raw_mgt_packet_received_bus	std_logic_vector ( 3 downto 0 )
raw_mgt_safe_mode_bus	std_logic_vector ( 3 downto 0 )
raw_mgt_packet_err_bus	std_logic_vector ( 3 downto 0 )
raw_mgt_length_err_bus	std_logic_vector ( 3 downto 0 )
raw_mgt_bcn_err_bus	std_logic_vector ( 3 downto 0 )
raw_mgt_last_l1id_bus	mgt_data_array ( 3 downto 0 )
mux_data_A_bus	packet_data_array ( 5 downto 0 )
mux_data_B_bus	packet_data_array ( 5 downto 0 )
mux_enable_A_bus	std_logic_vector ( 5 downto 0 )
mux_enable_B_bus	std_logic_vector ( 5 downto 0 )
mux_last_A_bus	std_logic_vector ( 5 downto 0 )
mux_last_B_bus	std_logic_vector ( 5 downto 0 )
mux_ready_A_bus	std_logic_vector ( 5 downto 0 )
mux_ready_B_bus	std_logic_vector ( 5 downto 0 )
mux_valid_A_bus	std_logic_vector ( 5 downto 0 )
mux_valid_B_bus	std_logic_vector ( 5 downto 0 )
mux_reset_A_bus	std_logic_vector ( 5 downto 0 )
mux_reset_B_bus	std_logic_vector ( 5 downto 0 )
mux_data_A_reg_bus	packet_data_array ( 5 downto 0 )
mux_data_B_reg_bus	packet_data_array ( 5 downto 0 )
mux_last_A_reg_bus	std_logic_vector ( 5 downto 0 )
mux_last_B_reg_bus	std_logic_vector ( 5 downto 0 )
mux_ready_A_reg_bus	std_logic_vector ( 5 downto 0 )
mux_ready_B_reg_bus	std_logic_vector ( 5 downto 0 )
mux_valid_A_reg_bus	std_logic_vector ( 5 downto 0 )
mux_valid_B_reg_bus	std_logic_vector ( 5 downto 0 )
mux_active_bus	std_logic_vector ( 1 downto 0 )
mux_l1id_valid_bus	std_logic_vector ( 1 downto 0 )
mux_source_bus	std_logic_vector ( 7 downto 0 )
mux_l1id_bus	mgt_data_array ( 1 downto 0 )
packet_data_bus	packet_data_array ( 1 downto 0 )
packet_builder_data_bus	packet_data_array ( 1 downto 0 )
built_data_bus	packet_data_array ( 1 downto 0 )
packet_last_bus	std_logic_vector ( 1 downto 0 )
packet_valid_bus	std_logic_vector ( 1 downto 0 )
packet_ready_bus	std_logic_vector ( 1 downto 0 )
built_last_bus	std_logic_vector ( 1 downto 0 )
built_valid_bus	std_logic_vector ( 1 downto 0 )
packet_builder_last_bus	std_logic_vector ( 1 downto 0 )
packet_builder_valid_bus	std_logic_vector ( 1 downto 0 )
packet_builder_ready_bus	std_logic_vector ( 1 downto 0 )
source_enable_sig	*std_logic_vector ( NProcessorFPGA 2 - 1 downto 0 ) := ( others = > ' 0 ' )**
raw_destination_select_sig	*std_logic_vector ( NProcessorFPGA 2 - 1 downto 0 ) := ( others = > ' 0 ' )**
tob_destination_enable_sig	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
bcr_40_tff	std_logic := ' 0 '
ecr_40_tff	std_logic := ' 0 '
bcr_320	std_logic := ' 0 '
ecr_320	std_logic := ' 0 '
bcr_320_tff_buf	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
ecr_320_tff_buf	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )

Attributes
ASYNC_REG	string
ASYNC_REG	signal is " TRUE "

Instantiations
mgt_object	mgt_buffer <Entity mgt_buffer>
tob_fifo_selector	fifo_selector <Entity fifo_selector>
tob_fifo_a	packet_fifo_block <Entity packet_fifo_block>
tob_register_a	fwft_register <Entity fwft_register>
tob_fifo_reset_a	packet_fifo_reset_block <Entity packet_fifo_reset_block>
tob_fifo_b	packet_fifo_block <Entity packet_fifo_block>
tob_register_b	fwft_register <Entity fwft_register>
tob_fifo_reset_b	packet_fifo_reset_block <Entity packet_fifo_reset_block>
ttc_fifos	ttc_fifo_block <Entity ttc_fifo_block>
tob_merge_a	efex_tob_merger <Entity efex_tob_merger>
tob_spy_a	tob_merger_spy <Entity tob_merger_spy>
tob_merge_b	efex_tob_merger <Entity efex_tob_merger>
tob_spy_b	tob_merger_spy <Entity tob_merger_spy>
merged_fifo_a	packet_fifo_block <Entity packet_fifo_block>
merged_fifo_reset_block_a	packet_fifo_reset_block <Entity packet_fifo_reset_block>
merged_fifo_b	packet_fifo_block <Entity packet_fifo_block>
merged_fifo_reset_block_b	packet_fifo_reset_block <Entity packet_fifo_reset_block>
mgt_object	mgt_buffer <Entity mgt_buffer>
raw_ram_fifo	packet_ram_fifo <Entity packet_ram_fifo>
raw_fifo_selector	fifo_selector <Entity fifo_selector>
raw_fifo_a	packet_fifo <Entity packet_fifo>
raw_fifo_b	packet_fifo <Entity packet_fifo>
raw_fifo_reset_block	packet_fifo_reset_block <Entity packet_fifo_reset_block>
mux_register_a	fwft_register <Entity fwft_register>
mux_register_b	fwft_register <Entity fwft_register>
packet_mux_a	efex_packet_mux <Entity efex_packet_mux>
packet_mux_b	efex_packet_mux <Entity efex_packet_mux>
packet_builder_register	fwft_register <Entity fwft_register>
packet_builder	efex_packet_builder <Entity efex_packet_builder>
built_fifo_spy	fifo_spy <Entity fifo_spy>
ipbusblock	packet_status_block <Entity packet_status_block>
srlc32e_reset_delay	srlc32e

Detailed Description

Instantiate the readout merging and routing logic...

Instantiate the readout merging and routing logic

Input is array of 8 MGT data streams in physical order (U1 to U4, first TOB then Input Data for each FPGA in turn). Output is array of 2 AXI stream outputs, 1 for each Aurora link

Input and output control are governed by source_enable (bit mask in Processor Number order, TOBs then Input Data) and (tob/raw)_destination_enable (the two RODs). Source enable is self explanatory, tob_destination_enable determines whether ping-pong is used or not, raw__destination_enable the mapping for Input Data Network is defined by sampling these immediately after rst_320 is deasserted.

All enable signals are gated with l1a_enable, including the FIFO write enable signals

The TOB data are rearranged into Processor Number order and mapped into an A and B bank of packet_fifo_blocks, with both output streams active odd events go to bank A, even to bank B, with only one active all events go to that bank.

Similarly the raw data are rearranged into Processor Number order and mapped into a single bank of packet_ram_fifos These cascade into an A and B bank of packet_fifos, with both output streams active odd MGT go to bank A, even to bank B, with only one active all MGT go to that bank.

The TTC FIFO data are routed into an A and B FIFO to match the TOB data routing.

There are then two instances of the TOB merger logic processing the banks A and B into two pairs of packet_fifo_blocks, one for merged packets the other the debug stream.

Finally there are two efex_packet_mux, one for each Aurora stream, each with associated efex_packet_builder and fifo_spy

Author: David Sankey

Definition at line 99 of file packet_block.vhd.

The documentation for this class was generated from the following file:

Infrastructure/control_fpga/src/data_path/packet_block.vhd

Components
efex_packet_builder	<Entity efex_packet_builder>
	FIFO signals.
efex_packet_mux	<Entity efex_packet_mux>
	towards Aurora readout
fwft_register	<Entity fwft_register>
	FIFO signals.
mgt_buffer	<Entity mgt_buffer>
efex_tob_merger	<Entity efex_tob_merger>
fifo_selector	<Entity fifo_selector>
packet_fifo_block	<Entity packet_fifo_block>
packet_ram_fifo	<Entity packet_ram_fifo>
packet_fifo	<Entity packet_fifo>
packet_fifo_reset_block	<Entity packet_fifo_reset_block>
ttc_fifo_block	<Entity ttc_fifo_block>
fifo_spy	<Entity fifo_spy>
tob_merger_spy	<Entity tob_merger_spy>
packet_status_block	<Entity packet_status_block>
SRLC32E

Processes

Components

Constants

Signals

Attributes

Instantiations

Detailed Description