cntrl_crc_checker.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.all;
library infrastructure_lib;
use infrastructure_lib.all;
 entity cntrl_crc_checker is
 port (
    clk         :in std_logic;
    reset        :in std_logic;
     mgt_enable        :in std_logic;
    mgt_commdet :in std_logic;
    rxdata      :in std_logic_vector(31 downto 0);
    crc_error   :out std_logic
    
    );
 
 end cntrl_crc_checker; 
 
 
 architecture behavioral of cntrl_crc_checker is
 
 
 constant REVERSE_BIT_ORDER : boolean := FALSE;
 signal start_rxcrc_i,crc_error_i : std_logic:='0';
 signal rx_data_i,rxdata_reg0,rxdata_reg1,rxdata_reg2  : std_logic_vector(31 downto 0):= x"00000000";
 signal rxdata_crc_in, rx_crc_i,rxdata_crc_reg   : std_logic_vector(8 downto 0):= "000000000";
  signal check_crc,latch_crc,crc_start_reg,crc_rdy_i : std_logic := '0';
 
 type state_type is (  idle,wt,high_crc  ) ;
 signal current_state : state_type;  
   
   
begin 
 
 
 pipe_rxdata_crc: process (clk)
           begin 
            if clk' event and clk ='1' then
               if latch_crc ='1' then
                   rxdata_crc_reg <= rxdata_crc_in;
               end if;
            end if;
         end process;  
 
 
pipe_rxdata: process (clk)
           begin 
            if clk' event and clk ='1' then
               rxdata_reg0 <= rxdata after 1 ns ;
               rxdata_reg1 <= rxdata_reg0 after 1 ns ;
               crc_start_reg <= start_rxcrc_i after 1 ns;
             end if;
            end process;  
 
 RX: entity work.osum_crc9d32
    generic map(
      REVERSE_BIT_ORDER => REVERSE_BIT_ORDER)
    port map (
 
      d_in       =>  rx_data_i,
      crc_start  =>  crc_start_reg and mgt_enable    ,
      clock      => clk,
      crc_out    => rx_crc_i
 
      );
 
crc_sm : entity infrastructure_lib.ttc_crc_sm 
   port map ( 
      clk           => clk,
      mgt_commdet   => mgt_commdet, 
      reset         => reset,
      mgt_enable    => mgt_enable,                 
      rxdata        => rxdata_reg1,   
      check_crc     => check_crc,  
      crc_data      => rx_data_i,                   
      latch_crc     => latch_crc ,                  
      rxdata_crc_in => rxdata_crc_in,                    
      start_crc     => start_rxcrc_i,
       crc_rdy     =>  crc_rdy_i
   );
                 
 
crc_error_i <= '1' when (rxdata_crc_reg /= rx_crc_i and (check_crc ='1')) else  '0';
crc_error <= crc_error_i;
 
 
 
 
 
 
 
 
 
 
 
 
end behavioral;