ttc_crc_sm Entity Reference

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Inheritance diagram for ttc_crc_sm:

Entities
fsm	architecture

Libraries
ieee

Use Clauses
std_logic_1164
std_logic_arith

Ports
clk	in	std_logic
		MGT rx clock of 160MHz.
mgt_commdet	in	std_logic
		MGT commadet.
mgt_enable	in	std_logic
reset	in	std_logic
		reset
rxdata	in	std_logic_vector ( 31 DOWNTO 0 )
		MGT TTC rx data.
check_crc	out	std_logic
		check crc ready
crc_data	out	std_logic_vector ( 31 DOWNTO 0 )
		crc input data
latch_crc	out	std_logic
		latch crc data
rxdata_crc_in	out	std_logic_vector ( 8 DOWNTO 0 )
		incoming data crc
start_crc	out	std_logic
		start calculating crc
crc_rdy	out	std_logic

Detailed Description

Definition at line 16 of file ttc_crc_sm.vhd.

Member Data Documentation

ieee

ieee

Library

Author

Mohammed Siyad

Definition at line 11 of file ttc_crc_sm.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/ttc_crc_sm.vhd