ttc_crc_sm.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity ttc_crc_sm is
   port( 
      clk           : in     std_logic;
      mgt_commdet   : in     std_logic;
      mgt_enable    : in     std_logic;
      reset         : in     std_logic;
      rxdata        : in     std_logic_vector (31 DOWNTO 0);
      check_crc     : out    std_logic;
      crc_data      : out    std_logic_vector (31 DOWNTO 0);
      latch_crc     : out    std_logic;
      rxdata_crc_in : out    std_logic_vector (8 DOWNTO 0);
      start_crc     : out    std_logic;
      crc_rdy       : out    std_logic
   );
 
 
end entity ttc_crc_sm ;
architecture fsm of ttc_crc_sm is
 
   type state_type is (
      idle,
      st0,
      st1,
      st2,
      st3,
      st4
   );
 
  signal current_state : state_type;
 
begin
 
   
   clocked_proc : process ( clk, reset)
   
   begin
      if (reset = '1') then
         current_state <= idle;
         check_crc <= '0';
         crc_data <= (others => '0');
         latch_crc <= '0';
         rxdata_crc_in <= (others => '0');
         start_crc <= '0';
         crc_rdy <= '0';
      elsif (clk'event and clk = '1') then
 
         case current_state is
            when idle => 
               latch_crc      <= '0';
               if (mgt_commdet ='1' and mgt_enable ='1') then 
                  current_state <= st0;
                 else
                  current_state <= idle;
               end if;
            when st0 => 
               start_crc <= '1';
--               crc_data <= rxdata(31 downto 8) & x"00";
              check_crc <= '0' ;
               latch_crc <= '0';
               current_state <= st1;
            when st1 => 
               start_crc <= '0';
               crc_data <= rxdata(31 downto 8) & x"00"; --crc_data  <= rxdata(31 downto 0);
               check_crc <= '1' ;
               latch_crc <= '0';
               current_state <= st2;
            when st2 => 
               crc_data <= rxdata(31 downto 0);
                check_crc <= '0' ;
                crc_rdy <= '1';
               current_state <= st3;
            when st3 =>  
               crc_data <= rxdata(31 downto 0);
               current_state <= st4;  
            when st4 => 
               crc_data <= "000000000" & rxdata(22 downto 0) ;
               rxdata_crc_in   <= rxdata (31 downto 23);
               latch_crc      <= '1';
               start_crc <= '1';
               crc_rdy <= '0';
              -- if (mgt_commdet ='1') then 
                  current_state <= st1;
             --  else
               --   current_state <= st4;
              -- end if;
            when others =>
               current_state <= idle;
         end case;
      end if;
   end process clocked_proc;
 
end architecture fsm;