cntrl_crc_checker Entity Reference

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Inheritance diagram for cntrl_crc_checker:

Entities
behavioral	architecture

Libraries
IEEE
infrastructure_lib

Use Clauses
STD_LOGIC_1164
std_logic_arith
all

Ports
clk	in	std_logic
		MGT rx clock of 160MHz.
reset	in	std_logic
		reset
mgt_enable	in	std_logic
		mgt_enbable
mgt_commdet	in	std_logic
		MGT commadet.
rxdata	in	std_logic_vector ( 31 downto 0 )
		MGT rx data.
crc_error	out	std_logic
		crc error

Detailed Description

Definition at line 13 of file cntrl_crc_checker.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/cntrl_crc_checker.vhd