behavioral Architecture Reference

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Processes
pipe_rxdata_crc	( clk )
pipe_rxdata	( clk )

Constants
REVERSE_BIT_ORDER	boolean := FALSE

Types
state_type	( idle , wt , high_crc )

Signals
start_rxcrc_i	std_logic := ' 0 '
crc_error_i	std_logic := ' 0 '
rx_data_i	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
rxdata_reg0	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
rxdata_reg1	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
rxdata_reg2	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
rxdata_crc_in	std_logic_vector ( 8 downto 0 ) := " 000000000 "
rx_crc_i	std_logic_vector ( 8 downto 0 ) := " 000000000 "
rxdata_crc_reg	std_logic_vector ( 8 downto 0 ) := " 000000000 "
check_crc	std_logic := ' 0 '
latch_crc	std_logic := ' 0 '
crc_start_reg	std_logic := ' 0 '
crc_rdy_i	std_logic := ' 0 '
current_state	state_type

Instantiations
rx	osum_crc9d32 <Entity osum_crc9d32>
crc_sm	ttc_crc_sm <Entity ttc_crc_sm>

Detailed Description

Definition at line 34 of file cntrl_crc_checker.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/cntrl_crc_checker.vhd