top_ctrl_synch.vhd File Reference

Top Synchronisation of the control FPGA. More...

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Entities
top_cntrl_synch	entity
	Top Synchronisation of the control FPGA. More...
Behavioral	architecture
	Top Synchronisation of the control FPGA. More...

Detailed Description

Top Synchronisation of the control FPGA.

This synchronisation block performs following task:

• It synchronises the data from the MGT(32 bits ) to the 40MHz TTC (128 bits) clock domain.
• It detects the start of the frame which is flagged by the MGT_commadet signal.
• It only implements the first stage of the synchronisation by measuring the time between the arrival of MGT_commadet and the rising edge of ttc_clk.
• It saves the delay value to register which can be accessed through ipbus.

Author

Mohammed Siyad

Definition in file top_ctrl_synch.vhd.