Top Synchronisation of the control FPGA. More...

Inheritance diagram for top_cntrl_synch:

Entities
Behavioral	architecture
	Top Synchronisation of the control FPGA. More...

Ports
rx_clk160	in	std_logic
		rx clock of the mgt
TTC_clk	in	std_logic
		ttc clk of 40MHz
reset	in	std_logic
		reset active high
enable_mgt	in	std_logic
		enable mgt rx register
MGT_Commadet	in	std_logic
		comma detected for incoming data
reg_sel	in	std_logic_vector ( 3 downto 0 )
		setting BC mux
mux_sel	in	std_logic_vector ( 3 downto 0 )
		setting the first stage mux
delay_num	out	std_logic_vector ( 3 downto 0 )
		counted delay on the first stage of the synchronisation
start	in	std_logic
		start pulse for the calibration to start
rx_resetdone	in	std_logic
		rx reset done of the MGT
reg128_latch	out	std_logic
		latch enable
data_out	out	std_logic_vector ( 128 downto 0 )
		data out of 128 bits
data_in	in	std_logic_vector ( 31 downto 0 )
		rx data in
crc_error_in	in	std_logic
		crc_error input

Detailed Description

Top Synchronisation of the control FPGA.

This synchronisation block performs following task:

It synchronises the data from the MGT(32 bits ) to the 40MHz TTC (128 bits) clock domain.
It detects the start of the frame which is flagged by the MGT_commadet signal.
It only implements the first stage of the synchronisation by measuring the time between the arrival of MGT_commadet and the rising edge of ttc_clk.
It saves the delay value to register which can be accessed through ipbus.

Definition at line 19 of file top_ctrl_synch.vhd.

The documentation for this class was generated from the following file:

Entities