Behavioral Architecture Reference

Top Synchronisation of the control FPGA. More...

Signals
latch_enable	std_logic
temp0	std_logic
temp1	std_logic
Reg_enable	std_logic
commdet_delay	std_logic
delay_cnt	std_logic_vector ( 3 downto 0 )
mux_cntrl	std_logic_vector ( 3 downto 0 )
data_delay	std_logic_vector ( 3 downto 0 )
data_out_int	std_logic_vector ( 128 downto 0 )
dataout	std_logic_vector ( 128 downto 0 )
temp2	std_logic
temp3	std_logic
ttc_redge	std_logic
ttc_20M	std_logic
bcn	std_logic_vector ( 4 downto 0 )
probe0	std_logic_vector ( 165 downto 0 )

Instantiations
dtype	d_type <Entity d_type>

Detailed Description

Top Synchronisation of the control FPGA.

This synchronisation block performs following task:

• It synchronises the data from the MGT(32 bits ) to the 40MHz TTC (128 bits) clock domain.
• It detects the start of the frame which is flagged by the MGT_commadet signal.
• It only implements the first stage of the synchronisation by measuring the time between the arrival of MGT_commadet and the rising edge of ttc_clk.
• It saves the delay value to register which can be accessed through ipbus.

Author

Mohammed Siyad

Definition at line 54 of file top_ctrl_synch.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/top_ctrl_synch.vhd