rtl Architecture Reference

Capture FIFO traffic into IPBus DPRAM64... More...

Processes
ipbus_ram_block	( clk_320 )
fifo_reg_block	( clk_320 )
ipbus_ram_reg_block	( clk_320 )

Components
ipbus_dpram64

Signals
IPBus_RAM_addr	std_logic_vector ( IPBUS_ADDR_WIDTH- 1 downto 0 )
IPBus_RAM_addr_i	std_logic_vector ( IPBUS_ADDR_WIDTH- 1 downto 0 )
IPBus_RAM_din	std_logic_vector ( 63 DOWNTO 0 )
IPBus_RAM_din_i	std_logic_vector ( 63 DOWNTO 0 )
fifo_data_i	std_logic_vector ( 63 DOWNTO 0 )
IPBus_RAM_we	std_logic
IPBus_RAM_we_i	std_logic
fifo_valid_i	std_logic
fifo_last_i	std_logic
fifo_tready_i	std_logic

Instantiations
ipbus_ram	ipbus_dpram64

Detailed Description

Capture FIFO traffic into IPBus DPRAM64...

Capture FIFO traffic into IPBus DPRAM64 spy RAM Address 0 contains address of last end of packet Control signal rst_ipbus_addr resets write pointer to start of RAM Control signal enables wraparound in RAM if set to '1', otherwise single pass after rst_ipbus_addr Support

Author

David Sankey

Definition at line 44 of file fifo_spy.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/fifo_spy.vhd