infrastructure_slaves_cntrl Entity Reference

control fpga infrastructure slaves More...

Inheritance diagram for infrastructure_slaves_cntrl:

Entities
Behavioral	architecture
	control fpga infrastructure slaves More...

Libraries
IEEE
ipbus_lib
infrastructure_lib

Use Clauses
STD_LOGIC_1164
ipbus
spi	Package <spi>
all
mgt_type	Package <mgt_type>
ipbus_decode_efex_cntrl_infrastructure	Package <ipbus_decode_efex_cntrl_infrastructure>

Ports
ipb_clk	in	std_logic
		IPBus clock.
ipb_rst	in	std_logic
		IPBus Reset input.
ipb_in	in	ipb_wbus
		IPBus input bus going from master to slaves.
ipb_out	out	ipb_rbus
		IPBus output bus going from slaves to master.
status	in	std_logic_vector ( 31 downto 0 )
		module status signals
control_reg	out	std_logic_vector ( 31 downto 0 )
		module control signals
reconfig_reg	out	std_logic_vector ( 31 downto 0 )
scl	out	std_logic
		i2c bus signals
sda_o	out	std_logic
sda_i	in	std_logic
pll_miso	in	std_logic
		spi pll input signals
pll_le	out	std_logic
		spi pll enable enable
pll_clko	out	std_logic
		spi pll clock
pll_mosi	out	std_logic
		spi pll output signals
pll_select	out	std_logic_vector ( 1 downto 0 )
		spi pll select
flash_miso	in	std_logic
		spi flash input signals
flash_le	out	std_logic
		spi flash enable
flash_clko	out	std_logic
		spi flash clock
flash_mosi	out	std_logic
		spi flash output signals
VAUXP	in	STD_LOGIC_VECTOR ( 5 downto 0 )
VAUXN	in	STD_LOGIC_VECTOR ( 5 downto 0 )
Vp	in	std_logic
Vn	in	std_logic

Detailed Description

control fpga infrastructure slaves

This slave infrastructure_slaves_cntrl comprises a collection of IPBus slaves of the control FPGAs. A slave being an interface between IPBus and the application logic. It implements a simple control or status register, an area of RAM that is mapped to IPBus, a state machine under IPBus control, or an interface to a second bus, such as SPI and XADC. The ipbus bus fabric, address select logic, data multiplexers This version selects the addressed slave depending on the state of incoming control lines. The ipbus slaves live in this entity and can be modified according to requirements. In the design ports can be added to give ipbus slaves access to the chip top level.

Author

Mohammed Siyad

Definition at line 24 of file infrastructure_slaves_cntrl.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/cntrl_slaves/infrastructure_slaves_cntrl.vhd