Behavioral Architecture Reference

control fpga infrastructure slaves More...

Signals
ipbw	ipb_wbus_array ( N_SLAVES- 1 downto 0 )
ipbr	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
ipbr_d	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
ctrl_pulse_reg	std_logic_vector ( 31 downto 0 )
pll_spi_in	spi_mi
flash_spi_in	spi_mi
pll_spi_out	spi_mo
flash_spi_out	spi_mo
flash_select	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )

Instantiations
fabric	ipbus_fabric_sel
module_control	ipbus_ctrlreg_v
xadc	ipbus_xadc_drp <Entity ipbus_xadc_drp>
reconfig	ipbus_ctrlreg_v
i2c_0	ipbus_i2c_master_arb <Entity ipbus_i2c_master_arb>
spi_pll	ipbus_spi32 <Entity ipbus_spi32>
spi_flash	ipbus_spi32 <Entity ipbus_spi32>
ram	ipbus_ram

Detailed Description

control fpga infrastructure slaves

This slave infrastructure_slaves_cntrl comprises a collection of IPBus slaves of the control FPGAs. A slave being an interface between IPBus and the application logic. It implements a simple control or status register, an area of RAM that is mapped to IPBus, a state machine under IPBus control, or an interface to a second bus, such as SPI and XADC. The ipbus bus fabric, address select logic, data multiplexers This version selects the addressed slave depending on the state of incoming control lines. The ipbus slaves live in this entity and can be modified according to requirements. In the design ports can be added to give ipbus slaves access to the chip top level.

Author

Mohammed Siyad

Definition at line 69 of file infrastructure_slaves_cntrl.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/cntrl_slaves/infrastructure_slaves_cntrl.vhd