infrastructure_slaves_cntrl.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
library ipbus_lib;
use ipbus_lib.ipbus.all;
use work.spi.all;
library infrastructure_lib;
use infrastructure_lib.all;
use infrastructure_lib.mgt_type.all;
use infrastructure_lib.ipbus_decode_efex_cntrl_infrastructure.all;
entity infrastructure_slaves_cntrl is
  port(
    ipb_clk : in  std_logic;
    ipb_rst : in  std_logic;
    ipb_in  : in  ipb_wbus;
    ipb_out : out ipb_rbus;
    status  : in  std_logic_vector(31 downto 0);
    control_reg : out std_logic_vector(31 downto 0);
    ---! reconfigure address
    reconfig_reg : out std_logic_vector(31 downto 0);
    scl    : out std_logic;
    sda_o   : out std_logic;
    sda_i   : in  std_logic;
    pll_miso   : in  std_logic;
    pll_le     : out std_logic;
    pll_clko   : out std_logic;
    pll_mosi   : out std_logic;
    pll_select : out std_logic_vector(1 downto 0);
    flash_miso : in  std_logic;
    flash_le   : out std_logic;
    flash_clko : out std_logic;
    flash_mosi : out std_logic;
    VAUXP, VAUXN       : in  STD_LOGIC_VECTOR (5 downto 0);
    Vp, Vn           : in std_logic
 
    );
 
end infrastructure_slaves_cntrl;
architecture Behavioral of infrastructure_slaves_cntrl is
 
 
 
--      constant sel_width:positive := 4;
  signal ipbw                       : ipb_wbus_array(N_SLAVES-1 downto 0);
  signal ipbr, ipbr_d               : ipb_rbus_array(N_SLAVES-1 downto 0);
  signal ctrl_pulse_reg             : std_logic_vector(31 downto 0);
  signal pll_spi_in, flash_spi_in   : spi_mi;
  signal pll_spi_out, flash_spi_out : spi_mo;
  signal flash_select               : std_logic_vector(1 downto 0) := (others => '0');
 
 
begin
 
 
--control_reg <= ctrl_pulse_reg ( 31 downto 0);
 
 
 
--- spi pll assignment
  pll_spi_in.miso <= pll_miso;
  pll_le          <= pll_spi_out.le;
  pll_mosi        <= pll_spi_out.mosi;
  pll_clko        <= pll_spi_out.clk;
 
--- spi flash pin assignment
  flash_spi_in.miso <= flash_miso;
  flash_mosi        <= flash_spi_out.mosi;
  flash_le          <= flash_spi_out.le;
  flash_clko        <= flash_spi_out.clk;
 
 
 
 
  fabric : entity ipbus_lib.ipbus_fabric_sel
    generic map(NSLV      => N_SLAVES,
                SEL_WIDTH => ipbus_sel_width)
    port map(
      ipb_in          => ipb_in,
      ipb_out         => ipb_out,
      sel             => ipbus_sel_efex_cntrl_infrastructure(ipb_in.ipb_addr),
      ipb_to_slaves   => ipbw,
      ipb_from_slaves => ipbr
      );
 
 
  module_control : entity ipbus_lib.ipbus_ctrlreg_v
    generic map (
      N_CTRL => 1,              --number of control reg
      N_STAT => 1)              --number of status reg
    port map (
      clk       => ipb_clk,
      reset     => ipb_rst,
      ipbus_in  => ipbw(N_SLV_MODULE_REG),
      ipbus_out => ipbr(N_SLV_MODULE_REG),
      d         => (0 => status),
      q(0)      => (control_reg),
--    qmask     => (others => '0'),
      stb       => open
      );
 
 
  xadc : entity work.ipbus_xadc_drp  -- accessing the xadc of the FPGA
    generic map (
      reg48 => X"4f01",
      reg49 => X"050f" )
    port map(
      ipb_clk   => ipb_clk,
      reset     => ipb_rst,
      VAUXP     => VAUXP,
      VAUXN     => VAUXN,
      Vp        => Vp,
      Vn        => Vn,
      ipbus_in  => ipbw(N_SLV_XADC),
      ipbus_out => ipbr(N_SLV_XADC)
 
      );
 
  reconfig : entity ipbus_lib.ipbus_ctrlreg_v
    generic map (
      N_CTRL => 1,                 --number of control reg
      N_STAT => 0)                 --number of status reg
    port map (
      clk       => ipb_clk,
      reset     => ipb_rst,
      ipbus_in  => ipbw(N_SLV_RECONFIGURE),
      ipbus_out => ipbr(N_SLV_RECONFIGURE),
      d         => (others =>(others => '0')),
      ctrl_default(0) => x"00020000",
      q(0)      => (reconfig_reg),
      stb       => open
      );
 
  i2c_0 : entity work.ipbus_i2c_master_arb
    generic map (addr_width => 4  -- slave that allow to access i2c devices that connect to i2c bus
                 )
    port map(
      clk         => ipb_clk,
      rst         => ipb_rst,
      ipb_in     => ipbw(N_SLV_I2C),
      ipb_out   => ipbr(N_SLV_I2C),
      scl          => scl,
      sda_o     => sda_o,
      sda_i      => sda_i
      );
 
 
  spi_pll : entity work.ipbus_spi32  -- Slave that used to configure the PLL and read its status
    generic map(
      BYTE_SPI   => false,
      ADDR_WIDTH => 6
      )
    port map(
      ipbus_clk => ipb_clk,
      reset     => ipb_rst,
      ipb_in    => ipbw(N_SLV_PLL_SPI_RAM),
      ipb_out   => ipbr(N_SLV_PLL_SPI_RAM),
      spi_in    => pll_spi_in,
      spi_out   => pll_spi_out,
      selreg    => pll_select
 
      );
 
  spi_flash : entity work.ipbus_spi32  --access to SPI FLASH for write/read it
    generic map(
      BYTE_SPI   => true,
      ADDR_WIDTH => 9
      )
    port map(
      ipbus_clk => ipb_clk,
      reset     => ipb_rst,
      ipb_in    => ipbw(N_SLV_FLASH_SPI_RAM),
      ipb_out   => ipbr(N_SLV_FLASH_SPI_RAM),
      spi_in    => flash_spi_in,
      spi_out   => flash_spi_out,
      selreg    => flash_select
 
      );
 
  RAM : entity ipbus_lib.ipbus_ram  -- internal ram for testing the iPbus transactions.
    generic map(
      ADDR_WIDTH => 10
      )
    port map(
      clk       => ipb_clk,
      reset     => ipb_rst,
      ipbus_in  => ipbw(N_SLV_RAM),
      ipbus_out => ipbr(N_SLV_RAM)
      );
 
end Behavioral;