spec Architecture Reference

This is the top level of the Control FPGA. More...

Processes
f5_ipbus_access_led_block	( mac_clk )
l1a_stretch_block	( clk40 )
reset_and_reboot_block	( ipb_clk )
reset_macclk_block	( mac_clk , clk_locked )
link_down_stretch	( mac_clk )
force_rx_error	( mac_clk )
reset_125_block	( mac_clk )
reset_clk40	( clk40 , locked )
IPBusReg	( mac_clk )
IPBusIO	( mac_clk )
ttcenable_pulse	( clk40 )
hub1_ila_error_block	( rx_clk160( 0 ) )
PROCESS_49	( clk40 )
PROCESS_50	( clk40 )
PROCESS_51	( clk40 )
PROCESS_52	( clk40 )
bcn_counter	( clk40 )
Aurora_link_control	( clk40 )
priv_rdout_block	( clk40 )
ttc_block	( clk40 )
ftm_ttc_mode_sel	( clk40 )
pipe_ttc	( clk40 )
ttc_rst_clk40	( clk40 )
ttc_rst_clk320	( clk320 )
reset_clk320	( clk320 )
busy_status_block	( ipb_clk )

Components
ila_0
ila_1
clk_ttc
axi_stream_fifo

Types
ttc_delay_array	array ( natural range <> ) of std_logic_vector ( 40 downto 0 )

Signals
efex_number	std_logic_vector ( 3 downto 0 )
clk125_fr	std_logic
clk200	std_logic
clk320	std_logic
clk160	std_logic
clko_p40	std_logic
ipb_clk	std_logic
mac_clk	std_logic
clk_locked	std_logic
eth_locked	std_logic
clk40	std_logic
clk280	std_logic
rx_clk280	std_logic_vector ( 7 downto 0 )
rst_125	std_logic
rst_ipb	std_logic
rst_eth	std_logic
rst_macclk	std_logic
sys_rst	std_logic
soft_rst	std_logic
rsto_eth	std_logic
enable_pll_rst	std_logic
reset_phy	std_logic := ' 1 '
pseudo_orbit	std_logic
mac_rx_data	std_logic_vector ( 7 downto 0 )
mac_rx_error	std_logic
mac_rx_valid	std_logic
mac_rx_last	std_logic
my_rx_error	std_logic
force_rx_error_buf	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
mac_tx_data	std_logic_vector ( 7 downto 0 )
mac_tx_error	std_logic
mac_tx_last	std_logic
mac_tx_ready	std_logic
mac_tx_valid	std_logic
onehz	std_logic
nuke	std_logic
rst_ipb_ctrl	std_logic
got_ip_address	std_logic
ipb_master_out	ipb_wbus
ipb_master_in	ipb_rbus
ipbw	ipb_wbus_array ( N_SLAVES- 1 downto 0 )
ipbr	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
ipbr_d	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
ipb_in	ipb_rbus
ipb_out	ipb_wbus
master_rx_data1_int	std_logic_vector ( 8 downto 0 )
master_rx_data2_int	std_logic_vector ( 8 downto 0 )
master_rx_data3_int	std_logic_vector ( 8 downto 0 )
master_rx_data4_int	std_logic_vector ( 8 downto 0 )
master_tx_data1_int	std_logic_vector ( 8 downto 0 )
master_tx_data2_int	std_logic_vector ( 8 downto 0 )
master_tx_data3_int	std_logic_vector ( 8 downto 0 )
master_tx_data4_int	std_logic_vector ( 8 downto 0 )
flash_clk	std_logic
flash_led	std_logic
scl_enb_0	std_logic
sda_enb_0	std_logic
scl_enb_1	std_logic
sda_enb_1	std_logic
scl_o_0	std_logic
sda_o_0	std_logic
scl_o_1	std_logic
sda_o_1	std_logic
Module_ID	std_logic_vector ( 31 downto 0 )
status	std_logic_vector ( 31 downto 0 )
master_tx_err1	std_logic
master_tx_err2	std_logic
master_tx_err3	std_logic
master_tx_err4	std_logic
control_reg	std_logic_vector ( 31 downto 0 )
pulse_reg	std_logic_vector ( 31 downto 0 )
reconfig_reg	std_logic_vector ( 31 downto 0 )
last_input_data_l1id	std_logic_vector ( 31 downto 0 )
input_data_readout_control	std_logic_vector ( 31 downto 0 )
clkfb_in	std_logic
gmii_rx_clk_int	std_logic
clkfb_out	std_logic
select_pll	std_logic_vector ( 1 downto 0 )
select_flash	std_logic_vector ( 1 downto 0 )
pll_en	std_logic
flash_csn_int	std_logic
trigger_reconfig	std_logic
reconfig	std_logic
en_reset	std_logic
data_reg0	std_logic
data_reg1	std_logic
reg128_latch	std_logic
flash_addr_int	std_logic_vector ( 2 downto 0 )
flash_mosi_int	std_logic
f5_flash_disable_int	std_logic
f5_flash_csn_int	std_logic
f1_flash_sel_int	std_logic
f2_flash_sel_int	std_logic
f3_flash_sel_int	std_logic
f4_flash_sel_int	std_logic
probe	std_logic_vector ( 12 downto 0 )
start	std_logic
hub1_rx_data	std_logic_vector ( 31 downto 0 )
hub2_rx_data	std_logic_vector ( 31 downto 0 )
rx_er_count	std_logic_vector ( 31 downto 0 )
hub1_combined_ttc_rxclk	std_logic_vector ( 128 downto 0 )
hub1_combined_ttc	std_logic_vector ( 128 downto 0 )
hub1_combined_ttc_i	std_logic_vector ( 128 downto 0 )
hub1_combined_ttc_ila	std_logic_vector ( 128 downto 0 )
hub2_combined_ttc_rxclk	std_logic_vector ( 128 downto 0 )
hub2_combined_ttc	std_logic_vector ( 128 downto 0 )
hub2_combined_ttc_i	std_logic_vector ( 128 downto 0 )
hub2_combined_ttc_ila	std_logic_vector ( 128 downto 0 )
hub1_combined_ttc_valid	std_logic
hub2_combined_ttc_valid	std_logic
mgt_enable	std_logic_vector ( 3 downto 0 )
bc_reg_sel	std_logic_vector ( 15 downto 0 )
mux_sel	std_logic_vector ( 15 downto 0 )
delay_cntr_0	std_logic_vector ( 3 downto 0 )
delay_cntr_1	std_logic_vector ( 3 downto 0 )
rx_resetdone_mgt114	std_logic_vector ( 1 downto 0 )
mgt_commadret	std_logic_vector ( 1 downto 0 )
rx_clk160	std_logic_vector ( 3 downto 0 )
RXN_IN_i	std_logic_vector ( 11 downto 0 )
RXP_IN_i	std_logic_vector ( 11 downto 0 )
encode_114	std_logic_vector ( 3 downto 0 )
rx_disperr_114	std_logic_vector ( 3 downto 0 )
ttc_BCR	std_logic
ttc_L1A	std_logic
ttc_ECR	std_logic
ttc_pr_rdout	std_logic
ttc_ECRID	std_logic_vector ( 7 downto 0 )
ttc_L1ID	std_logic_vector ( 23 downto 0 )
sof_topo_fpga1	std_logic
sof_topo_fpga2	std_logic
sof_topo_fpga3	std_logic
sof_topo_fpga4	std_logic
sof_raw_fpga1	std_logic
sof_raw_fpga2	std_logic
sof_raw_fpga3	std_logic
sof_raw_fpga4	std_logic
rx_resetdone	std_logic_vector ( 11 downto 0 )
tx_resetdone	std_logic_vector ( 11 downto 0 )
tx_fsm_resetdone	std_logic_vector ( 11 downto 0 )
rx_fsm_resetdone	std_logic_vector ( 11 downto 0 )
rx_realign	std_logic_vector ( 11 downto 0 )
rx_byteisaligned	std_logic_vector ( 11 downto 0 )
loopback	std_logic_vector ( 5 downto 0 )
rx_disperr	std_logic_vector ( 47 downto 0 )
encode_error	std_logic_vector ( 47 downto 0 )
qpll_lock	std_logic_vector ( 2 downto 0 )
qpll_refclklost	std_logic_vector ( 2 downto 0 )
softreset_tx	std_logic_vector ( 2 downto 0 )
softreset_rx	std_logic_vector ( 2 downto 0 )
tx_bufstatus	std_logic_vector ( 23 downto 0 )
gmii_rx_er_i	std_logic
hub2_combined_ttc_latch	std_logic
link_reset_hub1	std_logic
link_reset_hub2	std_logic
ttc_fifo_reset	std_logic
locked	std_logic := ' 0 '
reset	std_logic := ' 1 '
s_axi_tx_tdata_hub1	std_logic_vector ( 63 downto 0 )
s_axi_tx_tdata_data_hub1	std_logic_vector ( 63 downto 0 )
s_axi_tx_tdata_ufc_hub1	std_logic_vector ( 63 downto 0 )
s_axi_tx_tvalid_hub1	std_logic
s_axi_tx_tready_hub1	std_logic
s_axi_tx_tready_vld_hub1	std_logic
s_axi_tx_tlast_hub1	std_logic
s_axi_tx_tkeep_hub1	std_logic_vector ( 7 downto 0 )
s_axi_ufc_tx_req_hub1	std_logic
s_axi_ufc_tx_ack_hub1	std_logic
s_axi_ufc_tx_ms_hub1	std_logic_vector ( 2 downto 0 )
aurora_status_hub1	std_logic_vector ( 31 downto 0 )
tx_lane_up_hub1	std_logic_vector ( 3 downto 0 )
tx_channel_up_hub1	std_logic
tx_hard_err_hub1	std_logic
tx_lock_hub1	std_logic
pll_not_locked_hub1	std_logic
aurora_tx_resetdone_hub1	std_logic
aurora_user_clk_hub1	std_logic
sys_reset_out_hub1	std_logic
init_clk_out_hub1	std_logic
rd_rst_busy_hub1	std_logic
busy_status_hub1	std_logic_vector ( 15 downto 0 )
s_axi_tx_tdata_hub2	std_logic_vector ( 63 downto 0 )
s_axi_tx_tdata_data_hub2	std_logic_vector ( 63 downto 0 )
s_axi_tx_tdata_ufc_hub2	std_logic_vector ( 63 downto 0 )
s_axi_tx_tvalid_hub2	std_logic
s_axi_tx_tready_hub2	std_logic
s_axi_tx_tready_vld_hub2	std_logic
s_axi_tx_tlast_hub2	std_logic
s_axi_tx_tkeep_hub2	std_logic_vector ( 7 downto 0 )
s_axi_ufc_tx_req_hub2	std_logic
s_axi_ufc_tx_ack_hub2	std_logic
s_axi_ufc_tx_ms_hub2	std_logic_vector ( 2 downto 0 )
aurora_status_hub2	std_logic_vector ( 31 downto 0 )
tx_lane_up_hub2	std_logic_vector ( 3 downto 0 )
tx_channel_up_hub2	std_logic
tx_hard_err_hub2	std_logic
tx_lock_hub2	std_logic
pll_not_locked_hub2	std_logic
aurora_tx_resetdone_hub2	std_logic
aurora_user_clk_hub2	std_logic
sys_reset_out_hub2	std_logic
init_clk_out_hub2	std_logic
rd_rst_busy_hub2	std_logic
busy_status_hub2	std_logic_vector ( 15 downto 0 )
payload_data	std_logic_vector ( 63 downto 0 )
payload_valid	std_logic
payload_last	std_logic
tready_data	std_logic
first	std_logic
master_link_down_int	std_logic_vector ( 3 downto 0 )
master_link_down_dly	std_logic_vector ( 3 downto 0 )
fifo_empty	std_logic
valid	std_logic
rst_320	std_logic
rst_320_n	std_logic
bcn_cntr	std_logic_vector ( 11 downto 0 )
BCN	std_logic_vector ( 11 downto 0 )
ttc_din	std_logic_vector ( 49 downto 0 )
priv_rdout_l1id	std_logic_vector ( 23 downto 0 )
priv_rdout_reg_1	std_logic
priv_rdout_reg_2	std_logic
clk_mgt_bus	std_logic_vector ( N_PROCESSORFPGA * 2 - 1 downto 0 )
data_from_mgt_bus	mgt_data_array ( N_PROCESSORFPGA * 2 - 1 downto 0 )
char_is_k_bus	std_logic_vector ( N_PROCESSORFPGA * 2 - 1 downto 0 )
error_from_mgt_bus	std_logic_vector ( N_PROCESSORFPGA * 2 - 1 downto 0 )
payload_data_bus	packet_data_array ( 1 downto 0 )
payload_valid_bus	std_logic_vector ( 1 downto 0 )
payload_last_bus	std_logic_vector ( 1 downto 0 )
tready_data_bus	std_logic_vector ( 1 downto 0 )
tob_xoff_bus	std_logic_vector ( 1 downto 0 )
raw_xoff_bus	std_logic_vector ( 1 downto 0 )
mgt_xoff_bus	std_logic_vector ( N_PROCESSORFPGA * 2 - 1 downto 0 ) := ( others = > ' 0 ' )
merged_busy_bus	std_logic_vector ( N_PROCESSORFPGA * 2 - 1 downto 0 ) := ( others = > ' 0 ' )
processor_busy_bus	std_logic_vector ( N_PROCESSORFPGA * 2 - 1 downto 0 ) := ( others = > ' 0 ' )
local_busy_bus	std_logic_vector ( N_PROCESSORFPGA * 2 - 1 downto 0 ) := ( others = > ' 0 ' )
packet_mux_source	std_logic_vector ( 7 downto 0 )
TXN_OUT_i	std_logic_vector ( 11 downto 0 )
TXP_OUT_i	std_logic_vector ( 11 downto 0 )
ftm_ttc_mode	std_logic
phase2_ttc_mode	std_logic
phase2_ttc_delay_offset	std_logic_vector ( 1 downto 0 )
d_i	std_logic_vector ( 35 downto 0 )
e_i	std_logic_vector ( 35 downto 0 )
f_i	std_logic_vector ( 35 downto 0 )
g_i	std_logic_vector ( 35 downto 0 )
q_i	std_logic_vector ( 35 downto 0 )
ttc_l1A_i	std_logic_vector ( 3 downto 0 )
ttc_bcr_i	std_logic_vector ( 3 downto 0 )
ttc_ecr_i	std_logic_vector ( 3 downto 0 )
ttc_pr_rdout_i	std_logic_vector ( 3 downto 0 )
ttc_parity_i	std_logic_vector ( 3 downto 0 )
ttc_dummy_i	std_logic_vector ( 23 downto 0 ) := ( others = > ' 0 ' )
ttc_ECRID_i	std_logic_vector ( 31 downto 0 )
ttc_L1ID_i	std_logic_vector ( 95 downto 0 )
ttc_rst_tff	std_logic := ' 0 '
rst_320_tff_buf	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
hub1_ila_error_bit	std_logic
hub2_ila_error_bit	std_logic
parity12	std_logic
parity32	std_logic
xtal_ttc_sel	std_logic
force_priv_rdout	std_logic
crc_disable	std_logic
ttc_enable	std_logic
l1a_enable	std_logic
rod_override	std_logic_vector ( 1 downto 0 )
tob_aurora_en	std_logic_vector ( 1 downto 0 )
raw_aurora_en	std_logic_vector ( 1 downto 0 )
aurora_en	std_logic_vector ( 1 downto 0 )
tob_ro_en	std_logic_vector ( 3 downto 0 )
raw_ro_en	std_logic_vector ( 3 downto 0 )
p_fpga_reset_125	std_logic_vector ( 3 downto 0 )
master_tx1_int	std_logic_vector ( 9 downto 0 )
master_tx2_int	std_logic_vector ( 9 downto 0 )
master_tx3_int	std_logic_vector ( 9 downto 0 )
master_tx4_int	std_logic_vector ( 9 downto 0 )
master_tx1_reg	std_logic_vector ( 9 downto 0 )
master_tx2_reg	std_logic_vector ( 9 downto 0 )
master_tx3_reg	std_logic_vector ( 9 downto 0 )
master_tx4_reg	std_logic_vector ( 9 downto 0 )
master_pause1_int	std_logic
master_pause2_int	std_logic
master_pause3_int	std_logic
master_pause4_int	std_logic
master_pause1_reg	std_logic
master_pause2_reg	std_logic
master_pause3_reg	std_logic
master_pause4_reg	std_logic
master_rx1_int	std_logic_vector ( 9 downto 0 )
master_rx2_int	std_logic_vector ( 9 downto 0 )
master_rx3_int	std_logic_vector ( 9 downto 0 )
master_rx4_int	std_logic_vector ( 9 downto 0 )
master_rx1_reg	std_logic_vector ( 9 downto 0 )
master_rx2_reg	std_logic_vector ( 9 downto 0 )
master_rx3_reg	std_logic_vector ( 9 downto 0 )
master_rx4_reg	std_logic_vector ( 9 downto 0 )
slaves_ipbus_up_int	std_logic_vector ( 3 downto 0 )
dummy_tx1	std_logic_vector ( 49 downto 5 )
dummy_tx2	std_logic_vector ( 49 downto 5 )
dummy_tx3	std_logic_vector ( 49 downto 5 )
dummy_tx4	std_logic_vector ( 49 downto 5 )
dummy_rx1	std_logic_vector ( 54 downto 5 )
dummy_rx2	std_logic_vector ( 54 downto 5 )
dummy_rx3	std_logic_vector ( 54 downto 5 )
dummy_rx4	std_logic_vector ( 54 downto 5 )
i2c_sda_i	std_logic
sda_o	std_logic
image_type	std_logic
ttc_L1A_p	std_logic_vector ( 3 downto 0 )
ttc_L1A_n	std_logic_vector ( 3 downto 0 )
ttc_BCR_p	std_logic_vector ( 3 downto 0 )
ttc_BCR_n	std_logic_vector ( 3 downto 0 )
ttc_ECR_p	std_logic_vector ( 3 downto 0 )
ttc_ECR_n	std_logic_vector ( 3 downto 0 )
ttc_pr_rdout_p	std_logic_vector ( 3 downto 0 )
ttc_pr_rdout_n	std_logic_vector ( 3 downto 0 )
ttc_info_F1	std_logic_vector ( 37 downto 0 )
ttc_info_F2	std_logic_vector ( 37 downto 0 )
ttc_info_F3	std_logic_vector ( 37 downto 0 )
ttc_info_F4	std_logic_vector ( 37 downto 0 )
ttc_parity_F1	std_logic
ttc_parity_F2	std_logic
ttc_parity_F3	std_logic
ttc_parity_F4	std_logic
aurora_hub1_txp	std_logic_vector ( 3 downto 0 )
aurora_hub1_txn	std_logic_vector ( 3 downto 0 )
aurora_hub2_txp	std_logic_vector ( 3 downto 0 )
aurora_hub2_txn	std_logic_vector ( 3 downto 0 )
cntl_RAW_rdy_F1_out	std_logic
cntl_TOB_rdy_F1_out	std_logic
cntl_RAW_rdy_F2_out	std_logic
cntl_TOB_rdy_F2_out	std_logic
cntl_RAW_rdy_F3_out	std_logic
cntl_TOB_rdy_F3_out	std_logic
cntl_RAW_rdy_F4_out	std_logic
cntl_TOB_rdy_F4_out	std_logic
txp_OUT	std_logic_vector ( 9 downto 0 )
txn_OUT	std_logic_vector ( 9 downto 0 )
sk14	std_logic
sk15	std_logic
aurora_hub2_refclk1_p	std_logic
aurora_hub2_refclk1_n	std_logic
aurora_hub1_refclk1_p	std_logic
aurora_hub1_refclk1_n	std_logic
Q_CLK_GTREFCLK_PAD_N_IN	std_logic_vector ( 2 downto 0 )
Q_CLK_GTREFCLK_PAD_P_IN	std_logic_vector ( 2 downto 0 )
rxp_IN	std_logic_vector ( 9 downto 0 )
rxn_IN	std_logic_vector ( 9 downto 0 )
crc_error_i	std_logic_vector ( 1 downto 0 )
reg_temp0	std_logic
reg_temp1	std_logic
ttc_enable_pulse	std_logic
aurora_1_gt0_txctrl_i	std_logic_vector ( 23 downto 0 )
aurora_1_gt1_txctrl_i	std_logic_vector ( 23 downto 0 )
aurora_1_gt2_txctrl_i	std_logic_vector ( 23 downto 0 )
aurora_1_gt3_txctrl_i	std_logic_vector ( 23 downto 0 )
aurora_2_gt0_txctrl_i	std_logic_vector ( 23 downto 0 )
aurora_2_gt1_txctrl_i	std_logic_vector ( 23 downto 0 )
aurora_2_gt2_txctrl_i	std_logic_vector ( 23 downto 0 )
aurora_2_gt3_txctrl_i	std_logic_vector ( 23 downto 0 )

Attributes
DONT_TOUCH	string
DONT_TOUCH	signal is " TRUE "
ASYNC_REG	string
ASYNC_REG	signal is " TRUE "

Instantiations
global_ctrl_fabric	ipbus_fabric_sel
common_reg	common_id_registers <Entity common_id_registers>
u_0	top_udp_config_FPGA <Entity top_udp_config_FPGA>
u_1	interconnect <Entity interconnect>
u_2	interconnect <Entity interconnect>
u_3	interconnect <Entity interconnect>
u_4	interconnect <Entity interconnect>
clocks	clocks_7s_extphy <Entity clocks_7s_extphy>
eth	eth_7s_gmii <Entity eth_7s_gmii>
infrastructure_control	infrastructure_slaves_cntrl <Entity infrastructure_slaves_cntrl>
pll_sel	pll_selector <Entity pll_selector>
cclk_o	startup <Entity startup>
configure	reconfig <Entity reconfig>
ttc_clk	clk_ttc
reset_pll	nreset_pll <Entity nreset_pll>
mgt_tx_rx	top_mgt_cfpga <Entity top_mgt_cfpga>
synch_ttc_combined	top_cntrl_synch <Entity top_cntrl_synch>
crc_checker_hub1	cntrl_crc_checker <Entity cntrl_crc_checker>
crc_ila_hub1	ila_1
synch_hub2_combined_ttc	top_cntrl_synch <Entity top_cntrl_synch>
crc_checker_hub2	cntrl_crc_checker <Entity cntrl_crc_checker>
combined_ttc_ila	ila_0
srlc32e_inst_12	srlc32e
srlc32e_inst_12	srlc32e
srlc32e_inst_12	srlc32e
ttc_parity_calc	ttc_parity <Entity ttc_parity>
bcr	obufds
	ttc bcr fanout to the process fpgas
l1a	obufds
	ttc L1A fanout to the process fpgas
ecr	obufds
	ttc ecr fanout to the process fpgas
pr_rd	obufds
	ttc privilage read out fanout to the process fpgas
backplane_reg	backplane_registers <Entity backplane_registers>
mgt_slaves	mgt_cntrl_slaves <Entity mgt_cntrl_slaves>
readout_packet_block	packet_block <Entity packet_block>
hub1_axi_stream_fifo	axi_stream_fifo
hub1_ufc_block	ufc_controller <Entity ufc_controller>
hub2_axi_stream_fifo	axi_stream_fifo
hub2_ufc_block	ufc_controller <Entity ufc_controller>
output_channel1_ila	ila_0
output_channel2_ila	ila_0
top_aurora_hub1	aurora_hub2 <Entity aurora_hub2>
top_aurora_hub2	aurora_hub2 <Entity aurora_hub2>

Detailed Description

This is the top level of the Control FPGA.

Overview

The Control FPGA implements logic in three main functional areas:

• the real-time interface to the TTC
• the readout path
• the slow-control interface of the eFEX including support for the IPBus endpoints on the Processor FPGAs

Real-Time Logic

The TTC 40 MHz clock is received on a dedicated backplane channel, with the TTC information encoded on a second channel in the L1Calo backplane format. In terms of the TTC interface, the Control FPGA implements the following:

• It receives the data over one 6.4 Gb/s MGT link from the Hub module with fixed latency (the 6G4 part of top_mgt_cfpga) using the same first level synchronisation scheme as the Processor FPGAs (top_cntrl_synch)
• It decodes this TTC data and transmits the L1A, BCR, BCR, privileged readout, ECRID and L1ID signals synchronously as 40 MHz parallel signals to the processor FPGAs and buffers this information for use by the readout logic.

Readout Path

On the readout path, the Control FPGA performs the following functions:

• It receives TOB and calorimeter data from the four Processor FPGAs via a total of eight streams of 11.2 Gb/s data (the 11G2 part of top_mgt_cfpga)

The bulk of the readout logic is in packet_block:

• It buffers these data for flow control. (The main readout buffers on the eFEX are on the Processor FPGA. Correspondingly, the RAM resources required here are less than half of those on the Processor FPGAs).
• For the TOB readout it combines all of the data for an event into a single packet, for the Input Data the data for each FPGA remains in separate packets, then for each packet it adds header and trailer words that include TTC information and CRCs

Finally it sends the resultant packet to the L1Calo ROD via the Aurora interfaces that combine four 6.4Gb/s MGT lanes into a single channel to each ROD (aurora_hub2)

All of the above is under the control of a state machine which responds to back pressure from the L1Calo RODs, and can assert it to the Processor FPGAs and if need be assert BUSY.

Slow control and IPBus infrastructure

The control interface is implemented using IP from the IPBus project, which provides access to registers and RAM space within the firmware. For documentation on IPBus, see https://ipbus.web.cern.ch/introduction/

The IPBus infrastructure consists of:

• The Ethernet MAC clocks_7s_extphy and eth_7s_gmii (the Control FPGA is the only FPGA on the eFEX that has a physical connection to the Ethernet)
• top_udp_config_FPGA and interconnect (IPBus link layer to Processor FPGAs and local IPBus bus master on Control FPGA)

The local IPBus bus master interfaces to the following modules:

• common_id_registers (ID registers)
• infrastructure_slaves_cntrl (I2C and SPI interfaces)
• aurora_registers (control and status registers for the Aurora interface to the Hub-ROD)
• startup (Xilinx IP that provides a user interface FPGA configuration logic)
• self_configure (FPGA re-configuration control)
• pll_selector (generates PLL enable signals according to input selected)
• nreset_pll (generates reset for PLL)

  Author

  Mohammed Siyad

  David Sankey

Definition at line 182 of file top_efex_control.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/top/top_efex_control.vhd