eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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backplane_registers Entity Reference

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Inheritance diagram for backplane_registers:
cntr_generic top_efex_control

Entities

Behavioral  architecture
 

Libraries

IEEE 
ipbus_lib 
infrastructure_lib 

Use Clauses

STD_LOGIC_1164 
numeric_std 
ipbus 
ipbus_reg_types 
packet_mux_type  Package <packet_mux_type>
ipbus_decode_efex_cntrl_backplane  Package <ipbus_decode_efex_cntrl_backplane>

Ports

ipb_clk   in   std_logic
  ipbus clock
ipb_rst   in   std_logic
  ipbus reset
clk   in   std_logic
  TTC fabric clock.
rst   in   std_logic
  fabric reset
ipb_in   in   ipb_wbus
  IPBus input bus going from master to slaves.
ipb_out   out   ipb_rbus
  IPBus output bus going from slaves to master.
ttc_info   in   std_logic_vector ( 35 downto 0 )
  ttc_L1ID & ttc_ECRID & ttc_pr_rdout & ttc_ECR & ttc_BCR & ttc_L1A
aurora_status_1   in   std_logic_vector ( 31 downto 0 )
  aurora status hub1
aurora_1_gt0_txctl   out   std_logic_vector ( 23 downto 0 )
aurora_1_gt1_txctl   out   std_logic_vector ( 23 downto 0 )
aurora_1_gt2_txctl   out   std_logic_vector ( 23 downto 0 )
aurora_1_gt3_txctl   out   std_logic_vector ( 23 downto 0 )
aurora_status_2   in   std_logic_vector ( 31 downto 0 )
  aurora status hub2
aurora_2_gt0_txctl   out   std_logic_vector ( 23 downto 0 )
aurora_2_gt1_txctl   out   std_logic_vector ( 23 downto 0 )
aurora_2_gt2_txctl   out   std_logic_vector ( 23 downto 0 )
aurora_2_gt3_txctl   out   std_logic_vector ( 23 downto 0 )
control_xoff_bus   in   std_logic_vector ( 7 downto 0 )
  XOff and BUSY.
control_busy_bus   in   std_logic_vector ( 7 downto 0 )
processor_busy_bus   in   std_logic_vector ( 7 downto 0 )
input_data_readout_control   out   std_logic_vector ( 31 downto 0 )
  Privileged readout control.

Detailed Description

Definition at line 19 of file backplane_registers.vhd.


The documentation for this class was generated from the following file: