backplane_registers.vhd

Go to the documentation of this file.

 
 
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library ipbus_lib;
use ipbus_lib.ipbus.all;
use ipbus_lib.ipbus_reg_types.all;
library infrastructure_lib;
use infrastructure_lib.packet_mux_type.all;
use infrastructure_lib.ipbus_decode_efex_cntrl_backplane.all;
 
entity backplane_registers is
    port(
        ipb_clk : in std_logic;
        ipb_rst : in std_logic;
        clk : in std_logic;
        rst : in std_logic;
        ipb_in : in ipb_wbus;
        ipb_out : out ipb_rbus;
        ttc_info            : in std_logic_vector(35 downto 0);
        aurora_status_1 : in std_logic_vector(31 downto 0);
        aurora_1_gt0_txctl  : out std_logic_vector(23 downto 0);
        aurora_1_gt1_txctl  : out std_logic_vector(23 downto 0);
        aurora_1_gt2_txctl  : out std_logic_vector(23 downto 0);
        aurora_1_gt3_txctl  : out std_logic_vector(23 downto 0);
        aurora_status_2 : in std_logic_vector(31 downto 0);
        aurora_2_gt0_txctl  : out std_logic_vector(23 downto 0);
        aurora_2_gt1_txctl  : out std_logic_vector(23 downto 0);
        aurora_2_gt2_txctl  : out std_logic_vector(23 downto 0);
        aurora_2_gt3_txctl  : out std_logic_vector(23 downto 0);
        control_xoff_bus    : in std_logic_vector(7 downto 0); -- Processor Number order, (7 downto 4) Input Data (3 downto 0) TOBs
        control_busy_bus    : in std_logic_vector(7 downto 0); -- Processor Number order, (7 downto 4) Input Data (3 downto 0) TOBs
        processor_busy_bus  : in std_logic_vector(7 downto 0); -- Processor Number order, (7 downto 4) Input Data (3 downto 0) TOBs
        input_data_readout_control : out std_logic_vector(31 downto 0)
    );
 
end backplane_registers;
 
architecture Behavioral of backplane_registers is
 
    type integer_array is array(natural range <>) of integer range 0 to N_SLAVES;
--  mgt_data_array is array(natural range <>) of std_logic_vector(31 downto 0)
 
    signal ipbw: ipb_wbus_array(N_SLAVES-1 downto 0);
    signal ipbr: ipb_rbus_array(N_SLAVES-1 downto 0);
    signal aurora_status_bus: mgt_data_array(1 downto 0);
    signal aurora_gt_txctl_bus: mgt_data_array(7 downto 0);
    signal counter_control, bc_count, bc_count_ipb: std_logic_vector(31 downto 0);
    signal update_counter_reg_1, update_counter_reg_2, update_counter_reg_3, update_counter_bcr, update_counter_reg: std_logic;
    signal err_cntr_rst, status_cntr_rst, xoff_cntr_rst: std_logic;
-- TTC status
    signal ttc_bits: std_logic_vector(3 downto 0);
    signal ttc_counters, ttc_counters_ipb: mgt_data_array(3 downto 0);
    signal last_l1id, input_data_l1id, last_l1id_ipb, input_data_l1id_ipb: std_logic_vector(31 downto 0);
-- ROD link status
    signal rod_status, last_rod_status, rod_pulse: std_logic_vector(7 downto 0);
    signal rod1_tx_reset, rod2_tx_reset: std_logic_vector(1 downto 0);
    signal rod_counters, rod_counters_ipb: mgt_data_array(7 downto 0);
-- BUSY/XOff status
    signal control_xoff_reg, control_busy_reg, processor_busy_reg: std_logic_vector(15 downto 0);
    signal busy_xoff_bus_a, busy_xoff_bus_b, busy_xoff_bus_c, busy_xoff_reset_bus, busy_xoff_count_bus, busy_xoff_assert_bus: std_logic_vector(27 downto 0);
    signal busy_xoff_total_counter_bus, busy_xoff_active_counter_bus, busy_xoff_total_counter_bus_ipb, busy_xoff_active_counter_bus_ipb: mgt_data_array(27 downto 0);
    signal busy_xoff_assert_counter_bus, busy_xoff_assert_counter_bus_ipb: mgt_data_array(27 downto 0);
-- Mapping onto IPBus slave buses
    constant aurora_status_slv_bus: integer_array(1 downto 0) := (N_SLV_AURORA_STATUS_2, N_SLV_AURORA_STATUS_1);
    constant aurora_gt_txctl_slv_bus: integer_array(7 downto 0) := (
    N_SLV_AURORA2_GT3_TXCTRL, N_SLV_AURORA2_GT2_TXCTRL, N_SLV_AURORA2_GT1_TXCTRL, N_SLV_AURORA2_GT0_TXCTRL,
    N_SLV_AURORA1_GT3_TXCTRL, N_SLV_AURORA1_GT2_TXCTRL, N_SLV_AURORA1_GT1_TXCTRL, N_SLV_AURORA1_GT0_TXCTRL);
    constant rod_link_status_slv_bus: integer_array(1 downto 0) := (N_SLV_ROD_LINK_STATUS_ROD1, N_SLV_ROD_LINK_STATUS_ROD0);
    constant busy_xoff_slv_bus: integer_array(13 downto 0) := (
    N_SLV_PROCESSOR_BUSY_STATUS_P3, N_SLV_PROCESSOR_BUSY_STATUS_P2, N_SLV_PROCESSOR_BUSY_STATUS_P1, N_SLV_PROCESSOR_BUSY_STATUS_P0,
    N_SLV_CONTROL_BUSY_STATUS_P3, N_SLV_CONTROL_BUSY_STATUS_P2, N_SLV_CONTROL_BUSY_STATUS_P1, N_SLV_CONTROL_BUSY_STATUS_P0,
    N_SLV_CONTROL_XOFF_STATUS_P3, N_SLV_CONTROL_XOFF_STATUS_P2, N_SLV_CONTROL_XOFF_STATUS_P1, N_SLV_CONTROL_XOFF_STATUS_P0,
    N_SLV_BACKPLANE_XOFF_STATUS_ROD1, N_SLV_BACKPLANE_XOFF_STATUS_ROD0);
 
    attribute ASYNC_REG: string;
    attribute ASYNC_REG of rod1_tx_reset: signal is "TRUE";
    attribute ASYNC_REG of rod2_tx_reset: signal is "TRUE";
    attribute ASYNC_REG of control_xoff_reg: signal is "TRUE";
    attribute ASYNC_REG of control_busy_reg: signal is "TRUE";
    attribute ASYNC_REG of processor_busy_reg: signal is "TRUE";
 
begin
 
aurora_status_bus <= aurora_status_2 & aurora_status_1;
 
aurora_1_gt0_txctl<= aurora_gt_txctl_bus(0)(23 downto 0);
aurora_1_gt1_txctl<= aurora_gt_txctl_bus(1)(23 downto 0);
aurora_1_gt2_txctl<= aurora_gt_txctl_bus(2)(23 downto 0);
aurora_1_gt3_txctl<= aurora_gt_txctl_bus(3)(23 downto 0);
 
aurora_2_gt0_txctl<= aurora_gt_txctl_bus(4)(23 downto 0);
aurora_2_gt1_txctl<= aurora_gt_txctl_bus(5)(23 downto 0);
aurora_2_gt2_txctl<= aurora_gt_txctl_bus(6)(23 downto 0);
aurora_2_gt3_txctl<= aurora_gt_txctl_bus(7)(23 downto 0);
 
fabric_cntrl_backplane: entity ipbus_lib.ipbus_fabric_sel
    generic map(NSLV => N_SLAVES, SEL_WIDTH => IPBUS_SEL_WIDTH)
    port map(
        ipb_in => ipb_in,
        ipb_out => ipb_out,
        sel => ipbus_sel_efex_cntrl_backplane(ipb_in.ipb_addr),
        ipb_to_slaves => ipbw,
        ipb_from_slaves => ipbr
    );
 
control: entity ipbus_lib.ipbus_ctrlreg_v
    generic map (N_CTRL => 2, N_STAT => 1)
    port map(
        clk         => ipb_clk,
        reset       => ipb_rst,
        ipbus_in    => ipbw(N_SLV_CONTROL),
        ipbus_out   => ipbr(N_SLV_CONTROL),
        q(0)        => input_data_readout_control,
        q(1)        => counter_control,
        d(0)        => bc_count_ipb,
        ctrl_default(0) => x"0000c802",  -- Input Data every 200 events
        ctrl_default(1) => x"002bd702",  -- update at about 1 Hz
        stb         => open
    );
 
ttc_status: entity ipbus_lib.ipbus_ctrlreg_v
    generic map (N_CTRL => 0, N_STAT => 6)
    port map(
        clk         => ipb_clk,
        reset       => ipb_rst,
        ipbus_in    => ipbw(N_SLV_TTC_STATUS),
        ipbus_out   => ipbr(N_SLV_TTC_STATUS),
        q           => open,
        d(0)        => ttc_counters_ipb(0), -- L1A
        d(1)        => ttc_counters_ipb(3), -- privileged readout
        d(2)        => ttc_counters_ipb(1), -- BCR
        d(3)        => ttc_counters_ipb(2), -- ECR
        d(4)        => last_l1id_ipb,
        d(5)        => input_data_l1id_ipb,
        stb         => open
    );
 
aurora_status_generate_block: for i in 0 to 1 generate
    aurora_status: entity ipbus_lib.ipbus_ctrlreg_v
        generic map(N_CTRL => 0, N_STAT => 1)
        port map(
            clk         => ipb_clk,
            reset       => ipb_rst,
            ipbus_in    => ipbw(aurora_status_slv_bus(i)),
            ipbus_out   => ipbr(aurora_status_slv_bus(i)),
            d(0)        => aurora_status_bus(i),
            q           => open,
            stb         => open
        );
end generate aurora_status_generate_block;
 
aurora_gt_txctl_generate_block: for i in 0 to 7 generate
    aurora_gt_txctl: entity ipbus_lib.ipbus_ctrlreg_v
        generic map(N_CTRL => 1, N_STAT => 0)
        port map(
            clk         => ipb_clk,
            reset       => ipb_rst,
            ipbus_in    => ipbw(aurora_gt_txctl_slv_bus(i)),
            ipbus_out   => ipbr(aurora_gt_txctl_slv_bus(i)),
            d               => (others => (others => '0')),
            ctrl_default(0) => x"00000c07",
            q(0)            => aurora_gt_txctl_bus(i),
            stb         => open
        );
end generate aurora_gt_txctl_generate_block;
 
rod_link_status_generate_block: for i in 0 to 1 generate
    rod_link_status: entity ipbus_lib.ipbus_ctrlreg_v
        generic map (N_CTRL => 0, N_STAT => 4)
        port map(
            clk         => ipb_clk,
            reset       => ipb_rst,
            ipbus_in    => ipbw(rod_link_status_slv_bus(i)),
            ipbus_out   => ipbr(rod_link_status_slv_bus(i)),
            q           => open,
            d(0)        => rod_counters_ipb(i*4 + 2), -- rod_enable_count
            d(1)        => rod_counters_ipb(i*4 + 1), -- rod_up_count
            d(2)        => rod_counters_ipb(i*4), -- rod_reset_count
            d(3)        => rod_counters_ipb(i*4 + 3), -- rod_tx_reset_count
            stb         => open
        );
end generate rod_link_status_generate_block;
 
busy_xoff_status_generate_block: for i in 0 to 13 generate
    busy_xoff_status: entity ipbus_lib.ipbus_ctrlreg_v
        generic map (N_CTRL => 0, N_STAT => 6)
        port map(
            clk         => ipb_clk,
            reset       => ipb_rst,
            ipbus_in    => ipbw(busy_xoff_slv_bus(i)),
            ipbus_out   => ipbr(busy_xoff_slv_bus(i)),
            q           => open,
            d(0)        => busy_xoff_total_counter_bus_ipb(2*i), -- TOB
            d(1)        => busy_xoff_active_counter_bus_ipb(2*i),
            d(2)        => busy_xoff_assert_counter_bus_ipb(2*i),
            d(3)        => busy_xoff_total_counter_bus_ipb(2*i + 1), -- Raw
            d(4)        => busy_xoff_active_counter_bus_ipb(2*i + 1),
            d(5)        => busy_xoff_assert_counter_bus_ipb(2*i + 1),
            stb         => open
        );
end generate busy_xoff_status_generate_block;
 
update_counter_bcr_block: process(clk)
variable bcr_counter, bcr_match: unsigned(23 downto 0) := (Others => '0');
begin
    if rising_edge(clk) then
        bcr_match := unsigned(counter_control(31 downto 8));
        if (ttc_info(2) = '1') then -- ECR
            update_counter_bcr <= '0';
            bcr_counter := (Others => '0');
        elsif (ttc_info(1) = '1') then -- BCR
            if (bcr_counter >= bcr_match) then
                update_counter_bcr <= counter_control(1);
                bcr_counter := (Others => '0');
            else
                update_counter_bcr <= '0';
                bcr_counter := bcr_counter + 1;
            end if;
        else
            update_counter_bcr <= '0';
        end if;
    end if;
end process update_counter_bcr_block;
 
register_update_control: process(clk)
begin
    if rising_edge(clk) then
        update_counter_reg_1 <= counter_control(0);
        update_counter_reg_2 <= update_counter_reg_1;
        update_counter_reg_3 <= counter_control(2);
        if (update_counter_reg_1 = '1' and update_counter_reg_2 = '0') or (update_counter_reg_3 = '1') or (update_counter_bcr = '1') then
            update_counter_reg <= '1';
        else
            update_counter_reg <= '0';
        end if;
    end if;
end process register_update_control;
 
register_update: process(clk)
begin
    if rising_edge(clk) then
        if update_counter_reg = '1' then
            ttc_counters_ipb <= ttc_counters;
            last_l1id_ipb <= last_l1id;
            input_data_l1id_ipb <= input_data_l1id;
            rod_counters_ipb <= rod_counters;
            bc_count_ipb <= bc_count;
            busy_xoff_total_counter_bus_ipb <= busy_xoff_total_counter_bus;
            busy_xoff_active_counter_bus_ipb <= busy_xoff_active_counter_bus;
            busy_xoff_assert_counter_bus_ipb <= busy_xoff_assert_counter_bus;
        end if;
    end if;
end process register_update;
 
reset_control: process(clk)
begin
    if rising_edge(clk) then
        if (rst = '1') or (counter_control(4) = '1') then
            err_cntr_rst <= '1';
        else
            err_cntr_rst <= '0';
        end if;
        if (rst = '1') or (counter_control(5) = '1') then
            status_cntr_rst <= '1';
        else
            status_cntr_rst <= '0';
        end if;
        if (rst = '1') or (counter_control(6) = '1') then
            xoff_cntr_rst <= '1';
        else
            xoff_cntr_rst <= '0';
        end if;
    end if;
end process reset_control;
 
ttc_registers: process(clk)
begin
    if rising_edge(clk) then
        if (status_cntr_rst = '1') then
            last_l1id <= (Others => '0');
            input_data_l1id <= (Others => '0');
        elsif (ttc_info(0) = '1') then -- L1A
            last_l1id <= ttc_info(11 downto 4) & ttc_info(35 downto 12);
            if (ttc_info(3) = '1') then -- privileged readout
                input_data_l1id <= ttc_info(11 downto 4) & ttc_info(35 downto 12);
            end if;
        end if;
        ttc_bits(2 downto 0) <= ttc_info(2 downto 0);
        if (ttc_info(3) = '1') then -- only count privileged readout on L1A
            ttc_bits(3) <= ttc_info(0);
        else
            ttc_bits(3) <= '0';
        end if;
    end if;
end process ttc_registers;
 
ttc_counter_generate_block: for i in 0 to 3 generate
    ttc_counter_block : entity infrastructure_lib.cntr_generic
        generic map (width => 32, WRAPAROUND => False)
        port map (
            CE  => ttc_bits(i),
            CLK => clk,
            RST => status_cntr_rst,
            Q   => ttc_counters(i));
end generate ttc_counter_generate_block;
 
rod1_tx_reset_block: process(clk)
begin
    if rising_edge(clk) then
        rod1_tx_reset <= rod1_tx_reset(0) & aurora_status_1(8);
    end if;
end process rod1_tx_reset_block;
 
rod2_tx_reset_block: process(clk)
begin
    if rising_edge(clk) then
        rod2_tx_reset <= rod2_tx_reset(0) & aurora_status_2(8);
    end if;
end process rod2_tx_reset_block;
 
rod_registers: process(clk)
begin
    if rising_edge(clk) then
        if (status_cntr_rst = '1') then
            rod_status <= (Others => '0');
            last_rod_status <= (Others => '0');
            rod_pulse <= (Others => '0');
        else
            if (aurora_status_1(14) = '1') then -- cttc_valid
                rod_status(2 downto 0) <= aurora_status_1(13 downto 11); -- ROD enable & up & reset
            else
                rod_status(2 downto 0) <= rod_status(2 downto 0);
            end if;
            rod_status(3) <= rod1_tx_reset(1); -- tx_reset
            if (aurora_status_2(14) = '1') then -- cttc_valid
                rod_status(6 downto 4) <= aurora_status_2(13 downto 11); -- ROD enable & up & reset
            else
                rod_status(6 downto 4) <= rod_status(6 downto 4);
            end if;
            rod_status(7) <= rod2_tx_reset(1); -- tx_reset
        end if;
        last_rod_status <= rod_status;
        rod_pulse <= rod_status and not last_rod_status;
    end if;
end process rod_registers;
 
rod_counter_generate_block : for i in 0 to 7 generate
    rod_counter_block : entity infrastructure_lib.cntr_generic
        generic map (width => 32, WRAPAROUND => False)
        port map (
            CE  => rod_pulse(i),
            CLK => clk,
            RST => status_cntr_rst,
            Q   => rod_counters(i));
end generate rod_counter_generate_block;
 
bc_counter : entity infrastructure_lib.cntr_generic
    generic map (width => 32, WRAPAROUND => False)
    port map (
        CE  => '1',
        CLK => clk,
        RST => xoff_cntr_rst,
        Q   => bc_count
        );
 
control_xoff_block: process(clk)
begin
    if rising_edge(clk) then
        control_xoff_reg <= control_xoff_reg(7 downto 0) & control_xoff_bus;
    end if;
end process control_xoff_block;
 
control_busy_block: process(clk)
begin
    if rising_edge(clk) then
        control_busy_reg <= control_busy_reg(7 downto 0) & control_busy_bus;
    end if;
end process control_busy_block;
 
processor_busy_block: process(clk)
begin
    if rising_edge(clk) then
        processor_busy_reg <= processor_busy_reg(7 downto 0) & processor_busy_bus;
    end if;
end process processor_busy_block;
 
busy_xoff_registers: process(clk)
begin
    if rising_edge(clk) then
-- remap to pairs of Raw and TOB for each of Processor 3:0 BUSY, Control 3:0 BUSY, Control 3:0 XOff and ROD 1:0 XOff
        busy_xoff_bus_a(3 downto 0) <= aurora_status_2(10 downto 9) & aurora_status_1(10 downto 9); -- ROD 1 and 0, Raw and TOB
        busy_xoff_bus_a(11 downto 4) <= control_xoff_reg(15) & control_xoff_reg(11) & control_xoff_reg(14) & control_xoff_reg(10) & control_xoff_reg(13) & control_xoff_reg(9) & control_xoff_reg(12) & control_xoff_reg(8);
        busy_xoff_bus_a(19 downto 12) <= control_busy_reg(15) & control_busy_reg(11) & control_busy_reg(14) & control_busy_reg(10) & control_busy_reg(13) & control_busy_reg(9) & control_busy_reg(12) & control_busy_reg(8);
        busy_xoff_bus_a(27 downto 20) <= processor_busy_reg(15) & processor_busy_reg(11) & processor_busy_reg(14) & processor_busy_reg(10) & processor_busy_reg(13) & processor_busy_reg(9) & processor_busy_reg(12) & processor_busy_reg(8);
        busy_xoff_bus_b <= busy_xoff_bus_a;
        busy_xoff_bus_c <= busy_xoff_bus_b;
        busy_xoff_count_bus <= busy_xoff_bus_c; -- and delay the counters to be in sync after the reset for the active counters
        if (xoff_cntr_rst = '1') then
            busy_xoff_reset_bus <= (Others => '1');
            busy_xoff_assert_bus <= (Others => '0');
        else -- generate a reset for the active counters from transition from 0 to 1
            busy_xoff_reset_bus <= busy_xoff_bus_a and not busy_xoff_bus_b;
            busy_xoff_assert_bus <= busy_xoff_bus_a and not busy_xoff_bus_b;
        end if;
    end if;
end process busy_xoff_registers;
 
busy_xoff_counter_generate_block : for i in 0 to 27 generate
    total_counter_block : entity infrastructure_lib.cntr_generic
        generic map (width => 32, WRAPAROUND => False)
        port map (
            CE  => busy_xoff_count_bus(i),
            CLK => clk,
            RST => xoff_cntr_rst,
            Q   => busy_xoff_total_counter_bus(i));
 
    active_counter_block : entity infrastructure_lib.cntr_generic
        generic map (width => 32, WRAPAROUND => False)
        port map (
            CE  => busy_xoff_count_bus(i),
            CLK => clk,
            RST => busy_xoff_reset_bus(i),
            Q   => busy_xoff_active_counter_bus(i));
 
    assert_counter_block : entity infrastructure_lib.cntr_generic
        generic map (width => 32, WRAPAROUND => False)
        port map (
            CE  => busy_xoff_assert_bus(i),
            CLK => clk,
            RST => xoff_cntr_rst,
            Q   => busy_xoff_assert_counter_bus(i));
end generate busy_xoff_counter_generate_block;
 
end Behavioral;