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eFEX firmware
1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards
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Reset PLLs. More...
Entities | |
| Behavioral | architecture |
| Reset PLLs. More... | |
Libraries | |
| IEEE | |
Use Clauses | |
| STD_LOGIC_1164 | |
Ports | ||
| clk40 | in | std_logic |
| enable_pll_rst | in | std_logic |
| pll reset enable | ||
| rst_ipb | in | std_logic |
| SYNC_B_CDCE | out | std_logic |
| pll synch_b_CDCE | ||
Reset PLLs.
This generates active low PLL reset when enable_pll_rst is received through IPbus.
Definition at line 12 of file nreset_pll.vhd.
1.9.1