Behavioral Architecture Reference

Reset PLLs. More...

Processes
CDC	( clk40 , rst_ipb )
reg_pip	( clk40 )

Signals
data_reg1	std_logic
data_reg0	std_logic
SYNC_B_CDCE_int	std_logic

Instantiations
reset_gen	nreset_gen <Entity nreset_gen>

Detailed Description

Reset PLLs.

This generates active low PLL reset when enable_pll_rst is received through IPbus.

Author

Mohammed Siyad

Definition at line 27 of file nreset_pll.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/cntrl_slaves/nreset_pll.vhd