nreset_gen Entity Reference

Reset generation of PLLs. More...

Inheritance diagram for nreset_gen:

Entities
Behavioral	architecture
	Reset generation of PLLs. More...

Libraries
ieee

Use Clauses
std_logic_1164
std_logic_arith

Ports
clk	in	std_logic
		clock
en_rst	in	std_logic
		reset pll
reset	in	std_logic
		reset
nreset	out	std_logic
		active low pll reset

Detailed Description

Reset generation of PLLs.

This state machine generates reset signal when en_rst is received .

Author

Mohammed Siyad

Definition at line 12 of file nreset_gen.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/cntrl_slaves/nreset_gen.vhd