mgt_cntrl_slaves Entity Reference

MGT ipbus slave for control FPGA. More...

Inheritance diagram for mgt_cntrl_slaves:

Entities
Behavioral	architecture
	MGT ipbus slave for control FPGA. More...

Libraries
IEEE
ipbus_lib
infrastructure_lib

Use Clauses
STD_LOGIC_1164
NUMERIC_STD
ipbus
all
mgt_type	Package <mgt_type>
ipbus_decode_efex_cntrl_mgt	Package <ipbus_decode_efex_cntrl_mgt>

Ports
rx_clk160	in	std_logic_vector ( 3 downto 0 )
rx_clk280	in	std_logic_vector ( 7 downto 0 )
ipb_clk	in	std_logic
ipb_rst	in	std_logic
ipb_in	in	ipb_wbus
ipb_out	out	ipb_rbus
loopback	out	std_logic_vector ( 5 downto 0 )
softreset_tx	out	std_logic_vector ( 2 downto 0 )
softreset_rx	out	std_logic_vector ( 2 downto 0 )
qpll_lock	in	std_logic_vector ( 2 downto 0 )
qpll_refclklost	in	std_logic_vector ( 2 downto 0 )
rx_resetdone	in	std_logic_vector ( 11 downto 0 )
rx_fsm_resetdone	in	std_logic_vector ( 11 downto 0 )
rx_byteisaligned	in	std_logic_vector ( 11 downto 0 )
tx_resetdone	in	std_logic_vector ( 11 downto 0 )
tx_fsm_resetdone	in	std_logic_vector ( 11 downto 0 )
tx_bufstatus	in	std_logic_vector ( 23 downto 0 )
rx_realign	in	std_logic_vector ( 11 downto 0 )
rx_disperr	in	std_logic_vector ( 47 downto 0 )
encode_error	in	std_logic_vector ( 47 downto 0 )
bc_reg_sel	out	std_logic_vector ( 15 downto 0 )
delay_cntr_0	in	std_logic_vector ( 3 downto 0 )
delay_cntr_1	in	std_logic_vector ( 3 downto 0 )
mux_sel	out	std_logic_vector ( 15 downto 0 )
mgt_enable	out	std_logic_vector ( 3 downto 0 )
crc_error	in	std_logic_vector ( 1 downto 0 )

Detailed Description

MGT ipbus slave for control FPGA.

This Module combines all the slaves of the control MGTs in the design and connects to the ipbus registers. It uses ipbus fabric to select which quad slave to communicate through ipbus. It creates three quad slaves quad_0 for mgt 114, quad_1 for mgt 115 and quad_2 for mgt 116. Implements ipbus interface to the three quads in the design as follows:

• Control registers and status register of quad_0 for mgt 114
• Control registers and status register of quad_0 for mgt 115
• Control registers and status register of quad_0 for mgt 116

  Author

  Mohammed Syiad

Definition at line 26 of file mgt_cntrl_slaves.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/mgt/mgt_cntrl_slaves.vhd