eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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mgt_cntrl_slaves.vhd
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1 
12 
13 
14 
15 library IEEE;
16 use IEEE.STD_LOGIC_1164.ALL;
17 use IEEE.NUMERIC_STD.ALL;
18 library ipbus_lib;
19 use ipbus_lib.ipbus.all;
20 LIBRARY infrastructure_lib;
21 USE infrastructure_lib.all;
22 use infrastructure_lib.mgt_type.all;
23 use infrastructure_lib.ipbus_decode_efex_cntrl_mgt.all;
24 
26 entity mgt_cntrl_slaves is
27  Port (
28  rx_clk160 : in std_logic_vector(3 downto 0);
29  rx_clk280 : in std_logic_vector(7 downto 0);
30  ipb_clk : in std_logic;
31  ipb_rst : in std_logic;
32  ipb_in : in ipb_wbus;
33  ipb_out : out ipb_rbus;
34  --mgt quad
35  loopback : out std_logic_vector(5 downto 0);
36  softreset_tx : out std_logic_vector(2 downto 0);
37  softreset_rx : out std_logic_vector(2 downto 0);
38  qpll_lock : in std_logic_vector(2 downto 0);
39  qpll_refclklost : in std_logic_vector(2 downto 0);
40  rx_resetdone : in std_logic_vector (11 downto 0);
41  rx_fsm_resetdone : in std_logic_vector (11 downto 0);
42  rx_byteisaligned : in std_logic_vector (11 downto 0);
43  tx_resetdone : in std_logic_vector (11 downto 0);
44  tx_fsm_resetdone : in std_logic_vector (11 downto 0);
45  tx_bufstatus : in std_logic_vector (23 downto 0);
46  rx_realign : in std_logic_vector (11 downto 0);
47  rx_disperr : in std_logic_vector (47 downto 0);
48  encode_error : in std_logic_vector (47 downto 0);
49  bc_reg_sel : out std_logic_vector (15 downto 0);
50  delay_cntr_0 : in std_logic_vector (3 downto 0);
51  delay_cntr_1 : in std_logic_vector (3 downto 0);
52  mux_sel : out std_logic_vector (15 downto 0);
53  mgt_enable : out std_logic_vector(3 downto 0);
54  crc_error : in std_logic_vector(1 downto 0)
55 
56  );
57 
59 end mgt_cntrl_slaves;
60 
61 architecture Behavioral of mgt_cntrl_slaves is
62 
63 signal ipbw: ipb_wbus_array(N_SLAVES-1 downto 0);
64 signal ipbr, ipbr_d: ipb_rbus_array(N_SLAVES-1 downto 0);
65 signal txclk,txresetdone,txfsm_resetdone,mgt_enable_i : std_logic_vector(3 downto 0 );
66 signal mux_sel_i,bc_reg_sel_i : std_logic_vector(15 downto 0);
67 
68 begin
69 
70 --mux_sel <= mux_sel_i(7 downto 0);
71 --bc_reg_sel <= bc_reg_sel_i(16 downto 8);
72 --mgt_enable <= mgt_enable_i(1 downto 0);
73 
74 
75 
76 mgt_fabric : entity ipbus_lib.ipbus_fabric_sel
77  generic map(NSLV => N_SLAVES, --defined in ipbus_decode_mgt_slvs
78  SEL_WIDTH => ipbus_sel_width)
79  port map(
80  ipb_in => ipb_in,
81  ipb_out => ipb_out,
82  sel => ipbus_sel_efex_cntrl_mgt(ipb_in.ipb_addr),
83  ipb_to_slaves => ipbw,
84  ipb_from_slaves => ipbr
85  );
86 
87 quad_0: entity work.cntrl_mgt_quad_slaves
88  Port map (
89  clk280 => rx_clk160(3 downto 0),
90  ipb_clk => ipb_clk,
91  ipb_rst => ipb_rst ,
92  ipb_in => ipbw(N_SLV_MGT_114),
93  ipb_out => ipbr(N_SLV_MGT_114),
94  tx_pd => "0000", --tx power on
95  rx_pd => "1111", -- rx power on
96  loopback => loopback(5 downto 3),
97  bc_reg_sel => bc_reg_sel,
98  mux_sel => mux_sel,
99  bc_cntr_0 => (others => '0'),
100  bc_cntr_1 => (others => '0'),
101  bc_cntr_2 => (others => '0'),
102  bc_cntr_3 => (others => '0'),
103  bc_mux_cntr_0 => (others => '0'),
104  bc_mux_cntr_1 => (others => '0'),
105  bc_mux_cntr_2 => (others => '0'),
106  bc_mux_cntr_3 => (others => '0'),
107  delay_cntr_0 => delay_cntr_0, --(others => '0'),
108  delay_cntr_1 => delay_cntr_1, --(others => '0'),
109  delay_cntr_2 => (others => '0'), --delay_cntr_0 ,
110  delay_cntr_3 => (others => '0'), --delay_cntr_1 ,
111  softreset_tx => softreset_tx(2) ,
112  softreset_rx => softreset_rx(2) ,
113  mgt_enable => mgt_enable ,
114  phase_mux => open,
115  qpll_lock => qpll_lock(2),
116  qpll_refclklost => qpll_refclklost(2) ,
117  rx_resetdone => rx_resetdone(11 downto 8) ,
118  rx_fsm_resetdone => rx_fsm_resetdone(11 downto 8),
119  rx_byteisaligned => rx_byteisaligned(11 downto 8),
120  tx_resetdone => tx_resetdone(11 downto 8) ,
121  tx_fsm_resetdone => tx_fsm_resetdone(11 downto 8),
122  tx_bufstatus => tx_bufstatus(23 downto 16),
123  rx_realign => rx_realign(11 downto 8) ,
124  rx_disperr => rx_disperr(47 downto 32),
125  encode_error => encode_error(47 downto 32) ,
126  crc_error => crc_error
127  );
128 
129 quad_1: entity work.cntrl_mgt_quad_slaves
130  Port map (
131  clk280 => rx_clk280(3 downto 0),
132  ipb_clk => ipb_clk,
133  ipb_rst => ipb_rst ,
134  ipb_in => ipbw(N_SLV_MGT_115),
135  ipb_out => ipbr(N_SLV_MGT_115),
136  tx_pd => "0000", --- tx power on
137  rx_pd => "1111", --- rx power on
138  loopback => loopback(2 downto 0),
139  bc_reg_sel => open,
140  mux_sel => open,
141  bc_cntr_0 => (others => '0'),
142  bc_cntr_1 => (others => '0'),
143  bc_cntr_2 => (others => '0'),
144  bc_cntr_3 => (others => '0'),
145  bc_mux_cntr_0 => (others => '0'),
146  bc_mux_cntr_1 => (others => '0'),
147  bc_mux_cntr_2 => (others => '0'),
148  bc_mux_cntr_3 => (others => '0'),
149  delay_cntr_0 => (others => '0'),
150  delay_cntr_1 => (others => '0'),
151  delay_cntr_2 => (others => '0'),
152  delay_cntr_3 => (others => '0'),
153  softreset_tx => softreset_tx(0) ,
154  softreset_rx => softreset_rx(0) ,
155  mgt_enable => open ,
156  phase_mux => open,
157  qpll_lock => qpll_lock(0),
158  qpll_refclklost => qpll_refclklost(0) ,
159  rx_resetdone => rx_resetdone(3 downto 0) ,
160  rx_fsm_resetdone => rx_fsm_resetdone(3 downto 0),
161  rx_byteisaligned => rx_byteisaligned(3 downto 0),
162  tx_resetdone => tx_resetdone(3 downto 0) ,
163  tx_fsm_resetdone => tx_fsm_resetdone(3 downto 0),
164  tx_bufstatus => tx_bufstatus(7 downto 0),
165  rx_realign => rx_realign(3 downto 0) ,
166  rx_disperr => rx_disperr(15 downto 0),
167  encode_error => encode_error(15 downto 0) ,
168  crc_error => "00"
169  );
170 quad_2: entity work.cntrl_mgt_quad_slaves
171  Port map (
172  clk280 => rx_clk280(7 downto 4),
173  ipb_clk => ipb_clk,
174  ipb_rst => ipb_rst ,
175  ipb_in => ipbw(N_SLV_MGT_116),
176  ipb_out => ipbr(N_SLV_MGT_116),
177  tx_pd => "0000", --- tx power down
178  rx_pd => "1111", --- rx power on
179  loopback => open,
180  bc_reg_sel => open,
181  mux_sel => open,
182  bc_cntr_0 => (others => '0'),
183  bc_cntr_1 => (others => '0'),
184  bc_cntr_2 => (others => '0'),
185  bc_cntr_3 => (others => '0'),
186  bc_mux_cntr_0 => (others => '0'),
187  bc_mux_cntr_1 => (others => '0'),
188  bc_mux_cntr_2 => (others => '0'),
189  bc_mux_cntr_3 => (others => '0'),
190  delay_cntr_0 => (others => '0'),
191  delay_cntr_1 => (others => '0'),
192  delay_cntr_2 => (others => '0'),
193  delay_cntr_3 => (others => '0'),
194  softreset_tx => softreset_tx(1) ,
195  softreset_rx => softreset_rx(1) ,
196  mgt_enable => open,
197  phase_mux => open,
198  qpll_lock => qpll_lock(1),
199  qpll_refclklost => qpll_refclklost(1) ,
200  rx_resetdone => rx_resetdone(7 downto 4) ,
201  rx_fsm_resetdone => rx_fsm_resetdone(7 downto 4),
202  rx_byteisaligned => rx_byteisaligned(7 downto 4),
203  tx_resetdone => tx_resetdone(7 downto 4) ,
204  tx_fsm_resetdone => tx_fsm_resetdone(7 downto 4),
205  tx_bufstatus => tx_bufstatus(15 downto 8),
206  rx_realign => rx_realign(7 downto 4) ,
207  rx_disperr => rx_disperr(31 downto 16),
208  encode_error => encode_error(31 downto 16),
209  crc_error => "00"
210  );
211 
212 
213 
214 
215 end Behavioral;
cntrl_mgt_quad_slaves
MGT quad ipbus control.
Definition: cntrl_mgt_quad_slaves.vhd:16
ipbus_decode_efex_cntrl_mgt
Definition: ipbus_decode_efex_cntrl_mgt.vhd:14
mgt_cntrl_slaves.Behavioral
MGT ipbus slave for control FPGA.
Definition: mgt_cntrl_slaves.vhd:61
mgt_cntrl_slaves
MGT ipbus slave for control FPGA.
Definition: mgt_cntrl_slaves.vhd:26
mgt_type
Definition: mgt_type_pkg.vhd:4
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