Behavioral Architecture Reference

MGT ipbus slave for control FPGA. More...

Signals
ipbw	ipb_wbus_array ( N_SLAVES- 1 downto 0 )
ipbr	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
ipbr_d	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
txclk	std_logic_vector ( 3 downto 0 )
txresetdone	std_logic_vector ( 3 downto 0 )
txfsm_resetdone	std_logic_vector ( 3 downto 0 )
mgt_enable_i	std_logic_vector ( 3 downto 0 )
mux_sel_i	std_logic_vector ( 15 downto 0 )
bc_reg_sel_i	std_logic_vector ( 15 downto 0 )

Instantiations
mgt_fabric	ipbus_fabric_sel
quad_0	cntrl_mgt_quad_slaves <Entity cntrl_mgt_quad_slaves>
quad_1	cntrl_mgt_quad_slaves <Entity cntrl_mgt_quad_slaves>
quad_2	cntrl_mgt_quad_slaves <Entity cntrl_mgt_quad_slaves>

Detailed Description

MGT ipbus slave for control FPGA.

This Module combines all the slaves of the control MGTs in the design and connects to the ipbus registers. It uses ipbus fabric to select which quad slave to communicate through ipbus. It creates three quad slaves quad_0 for mgt 114, quad_1 for mgt 115 and quad_2 for mgt 116. Implements ipbus interface to the three quads in the design as follows:

• Control registers and status register of quad_0 for mgt 114
• Control registers and status register of quad_0 for mgt 115
• Control registers and status register of quad_0 for mgt 116

  Author

  Mohammed Syiad

Definition at line 61 of file mgt_cntrl_slaves.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/mgt/mgt_cntrl_slaves.vhd