cntrl_mgt_quad_slaves Entity Reference

MGT quad ipbus control. More...

Inheritance diagram for cntrl_mgt_quad_slaves:

Entities
Behavioral	architecture
	MGT quad ipbus control. More...

Libraries
IEEE
ipbus_lib

Use Clauses
STD_LOGIC_1164
numeric_std
ipbus
ipbus_decode_efex_cntrl_mgt_quad	Package <ipbus_decode_efex_cntrl_mgt_quad>

Ports
clk280	in	std_logic_vector ( 3 downto 0 )
ipb_clk	in	std_logic
ipb_rst	in	std_logic
ipb_in	in	ipb_wbus
ipb_out	out	ipb_rbus
loopback	out	std_logic_vector ( 2 downto 0 )
bc_reg_sel	out	std_logic_vector ( 15 downto 0 )
mux_sel	out	std_logic_vector ( 15 downto 0 )
softreset_tx	out	std_logic
softreset_rx	out	std_logic
qpll_lock	in	std_logic
qpll_refclklost	in	std_logic
tx_pd	in	std_logic_vector ( 3 downto 0 )
rx_pd	in	std_logic_vector ( 3 downto 0 )
bc_cntr_0	in	std_logic_vector ( 4 downto 0 )
bc_cntr_1	in	std_logic_vector ( 4 downto 0 )
bc_cntr_2	in	std_logic_vector ( 4 downto 0 )
bc_cntr_3	in	std_logic_vector ( 4 downto 0 )
bc_mux_cntr_0	in	std_logic_vector ( 4 downto 0 )
bc_mux_cntr_1	in	std_logic_vector ( 4 downto 0 )
bc_mux_cntr_2	in	std_logic_vector ( 4 downto 0 )
bc_mux_cntr_3	in	std_logic_vector ( 4 downto 0 )
delay_cntr_0	in	std_logic_vector ( 3 downto 0 )
delay_cntr_1	in	std_logic_vector ( 3 downto 0 )
delay_cntr_2	in	std_logic_vector ( 3 downto 0 )
delay_cntr_3	in	std_logic_vector ( 3 downto 0 )
mgt_enable	out	std_logic_vector ( 3 downto 0 )
phase_mux	out	std_logic_vector ( 15 downto 0 )
rx_resetdone	in	std_logic_vector ( 3 downto 0 )
rx_fsm_resetdone	in	std_logic_vector ( 3 downto 0 )
rx_byteisaligned	in	std_logic_vector ( 3 downto 0 )
tx_resetdone	in	std_logic_vector ( 3 downto 0 )
tx_fsm_resetdone	in	std_logic_vector ( 3 downto 0 )
tx_bufstatus	in	std_logic_vector ( 7 downto 0 )
rx_realign	in	std_logic_vector ( 3 downto 0 )
rx_disperr	in	std_logic_vector ( 15 downto 0 )
encode_error	in	std_logic_vector ( 15 downto 0 )
crc_error	in	std_logic_vector ( 1 downto 0 )

Detailed Description

MGT quad ipbus control.

Module to connect the single MGT to ipbus registers

Author

Mohammed Syiad

Francesco Gonnella

Definition at line 16 of file cntrl_mgt_quad_slaves.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd