eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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cntrl_mgt_quad_slaves.vhd
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1 
7 
8 library IEEE;
9 use IEEE.STD_LOGIC_1164.all;
10 use ieee.numeric_std.all;
11 library ipbus_lib;
12 use ipbus_lib.ipbus.all;
13 use work.ipbus_decode_efex_cntrl_mgt_quad.all;
14 
16 entity cntrl_mgt_quad_slaves is
17  port (
18  clk280 : in std_logic_vector(3 downto 0);
19  ipb_clk : in std_logic;
20  ipb_rst : in std_logic;
21  ipb_in : in ipb_wbus;
22  ipb_out : out ipb_rbus;
23  loopback : out std_logic_vector(2 downto 0);
24  bc_reg_sel : out std_logic_vector(15 downto 0);
25  mux_sel : out std_logic_vector(15 downto 0);
26  softreset_tx : out std_logic;
27  softreset_rx : out std_logic;
28  qpll_lock : in std_logic;
29  qpll_refclklost : in std_logic;
30  tx_pd : in std_logic_vector(3 downto 0);
31  rx_pd : in std_logic_vector(3 downto 0);
32  bc_cntr_0 : in std_logic_vector(4 downto 0);
33  bc_cntr_1 : in std_logic_vector(4 downto 0);
34  bc_cntr_2 : in std_logic_vector(4 downto 0);
35  bc_cntr_3 : in std_logic_vector(4 downto 0);
36  bc_mux_cntr_0 : in std_logic_vector(4 downto 0);
37  bc_mux_cntr_1 : in std_logic_vector(4 downto 0);
38  bc_mux_cntr_2 : in std_logic_vector(4 downto 0);
39  bc_mux_cntr_3 : in std_logic_vector(4 downto 0);
40  delay_cntr_0 : in std_logic_vector (3 downto 0);
41  delay_cntr_1 : in std_logic_vector (3 downto 0);
42  delay_cntr_2 : in std_logic_vector (3 downto 0);
43  delay_cntr_3 : in std_logic_vector (3 downto 0);
44  mgt_enable : out std_logic_vector(3 downto 0);
45  phase_mux : out std_logic_vector(15 downto 0);
46  rx_resetdone : in std_logic_vector (3 downto 0);
47  rx_fsm_resetdone : in std_logic_vector (3 downto 0);
48  rx_byteisaligned : in std_logic_vector (3 downto 0);
49  tx_resetdone : in std_logic_vector (3 downto 0);
50  tx_fsm_resetdone : in std_logic_vector (3 downto 0);
51  tx_bufstatus : in std_logic_vector (7 downto 0);
52  rx_realign : in std_logic_vector (3 downto 0);
53  rx_disperr : in std_logic_vector (15 downto 0);
54  encode_error : in std_logic_vector (15 downto 0);
55  crc_error : in std_logic_vector (1 downto 0)
56 
57 
58 
59  );
60 end cntrl_mgt_quad_slaves;
61 
63 architecture Behavioral of cntrl_mgt_quad_slaves is
64 --constant N_SLAVES: positive := 5;
65  signal ipbw : ipb_wbus_array(N_SLAVES-1 downto 0);
66  signal ipbr, ipbr_d : ipb_rbus_array(N_SLAVES-1 downto 0);
67  signal error_counter_reset : std_logic;
68  signal encode_error_int, rx_disperr_int : std_logic_vector (3 downto 0);
69  signal softreset_rx_int, softreset_tx_int, error_counter_reset_int : std_logic;
70  signal control_reg, synch_reg, pulse_reg, quad_status, phase_reg : std_logic_vector (31 downto 0);
71  signal pulse_reset, softreset_rx_i, error_counter_reset_i, softreset_tx_i : std_logic;
72  signal clr_pulse_reg, cntr_reset : std_logic;
73 
74 begin
75 --- quad fabric decoder
76 
77  fabric_quad : entity ipbus_lib.ipbus_fabric_sel
78  generic map(NSLV => N_SLAVES,
79  SEL_WIDTH => ipbus_sel_width)
80  port map(
81  ipb_in => ipb_in,
82  ipb_out => ipb_out,
83  sel => ipbus_sel_efex_cntrl_mgt_quad(ipb_in.ipb_addr),
84  ipb_to_slaves => ipbw,
85  ipb_from_slaves => ipbr
86  );
87 
88 
89 
90  encode_error_int(0) <= encode_error(0) or encode_error(1) or encode_error(2) or encode_error(3);
91  encode_error_int(1) <= encode_error(4) or encode_error(5) or encode_error(6) or encode_error(7);
92  encode_error_int(2) <= encode_error(8) or encode_error(9) or encode_error(10) or encode_error(11);
93  encode_error_int(3) <= encode_error(12) or encode_error(13) or encode_error(14) or encode_error(15);
94 
95  rx_disperr_int(0) <= rx_disperr(0) or rx_disperr(1) or rx_disperr(2) or rx_disperr(3);
96  rx_disperr_int(1) <= rx_disperr(4) or rx_disperr(5) or rx_disperr(6) or rx_disperr(7);
97  rx_disperr_int(2) <= rx_disperr(8) or rx_disperr(9) or rx_disperr(10) or rx_disperr(11);
98  rx_disperr_int(3) <= rx_disperr(12) or rx_disperr(13) or rx_disperr(14) or rx_disperr(15);
99 
100  loopback <= control_reg(2 downto 0); --- loopback signal
101  mgt_enable <= control_reg(7 downto 4); -- mgt enable signals
102  bc_reg_sel <= synch_reg (15 downto 0);
103  mux_sel <= synch_reg (31 downto 16);
104  softreset_tx_int <= pulse_reg(0); -- tx reset pulse
105  softreset_rx_int <= pulse_reg(1); -- rxreset pulse
106  error_counter_reset_int <= pulse_reg(2); -- error counter reset pulse
107  quad_status <= x"0000000" & "00" & qpll_refclklost & qpll_lock; --- concatenating the pll status signals
108  softreset_tx <= softreset_tx_i;
109  softreset_rx <= softreset_rx_i;
110  phase_mux <= phase_reg(15 downto 0);
111 
112  softreset_rx_pulse : entity work.led_stretch -- softresetrx pulse generator
113  port map(
114  input => softreset_rx_int,
115  clk => ipb_clk,
116 
117  output => softreset_rx_i
118  );
119 
120  softreset_tx_pulse : entity work.led_stretch -- softresettx pulse generator
121  port map(
122  input => softreset_tx_int,
123  clk => ipb_clk,
124  output => softreset_tx_i
125  );
126 
127  error_counter_reset_pulse : entity work.led_stretch -- pulse generator
128  port map(
129  input => error_counter_reset_int,
130  clk => ipb_clk,
131  output => error_counter_reset_i
132  );
133 
134  cntr_reset <= error_counter_reset_i or softreset_rx_i; -- error counter will be reset when rx is reset
135  pulse_reset <= softreset_rx_i or error_counter_reset_i or softreset_tx_i;
136  clr_pulse_reg <= ipb_rst or pulse_reset; -- reset the pulse register with ipb reset or when it generates one pulse
137 
138  MGT_QUAD_Control : entity ipbus_lib.ipbus_ctrlreg_v --- control register
139  generic map (
140  N_CTRL => 1, --number of control reg
141  N_STAT => 0) --number of status reg
142  port map(
143  clk => ipb_clk,
144  reset => ipb_rst,
145  ipbus_in => ipbw(N_SLV_QUAD_MGT_CONTROL),
146  ipbus_out => ipbr(N_SLV_QUAD_MGT_CONTROL),
147  d => (others => (others => '0')),
148  q(0) => control_reg,
149  stb => open);
150 
151  MGT_QUAD_Synch : entity ipbus_lib.ipbus_ctrlreg_v -- reads the module ID register
152  generic map (
153  N_CTRL => 1, --number of control reg
154  N_STAT => 0) --number of status reg
155  port map(
156  clk => ipb_clk,
157  reset => ipb_rst,
158  ipbus_in => ipbw(N_SLV_QUAD_SYNCH_CONTROL),
159  ipbus_out => ipbr(N_SLV_QUAD_SYNCH_CONTROL),
160  d => (others => (others => '0')),
161  q(0) => synch_reg,
162  stb => open);
163 
164  MGT_QUAD_Pulse : entity ipbus_lib.ipbus_ctrlreg_v -- reads the module ID register
165  generic map (
166  N_CTRL => 1, --number of control reg
167  N_STAT => 0) --number of status reg
168  port map(
169  clk => ipb_clk,
170  reset => clr_pulse_reg,
171  ipbus_in => ipbw(N_SLV_QUAD_MGT_PULSE),
172  ipbus_out => ipbr(N_SLV_QUAD_MGT_PULSE),
173  d => (others => (others => '0')),
174  q(0) => pulse_reg,
175  stb => open);
176 
177  MGT_QUAD_status : entity ipbus_lib.ipbus_ctrlreg_v
178  generic map (
179  N_CTRL => 0, --number of control reg
180  N_STAT => 1) --number of status reg
181  port map(
182  clk => ipb_clk,
183  reset => ipb_rst,
184  ipbus_in => ipbw(N_SLV_QUAD_MGT_STATUS),
185  ipbus_out => ipbr(N_SLV_QUAD_MGT_STATUS),
186  d => (0 => quad_status),
187  q => open,
188  stb => open);
189 
190  MGT_GT0 : entity work.gt_information
191  generic map (addr_width => 3)
192  port map(
193  ipb_clk => ipb_clk,
194  clk280 => clk280(0),
195  ipb_rst => ipb_rst,
196  reset => cntr_reset,
197  ipb_in => ipbw(N_SLV_GT0),
198  ipb_out => ipbr(N_SLV_GT0),
199  tx_pd => tx_pd(0),
200  rx_pd => rx_pd(0),
201  bc_cntr => bc_cntr_0,
202  bc_mux_cntr => bc_mux_cntr_0,
203  delay_cntr => delay_cntr_0,
204  not_intable => encode_error_int(0),
205  rx_resetdone => rx_resetdone(0),
206  rx_fsm_resetdone => rx_fsm_resetdone(0),
207  rx_byteisaligned => rx_byteisaligned(0),
208  tx_resetdone => tx_resetdone(0),
209  tx_fsm_resetdone => tx_fsm_resetdone(0),
210  tx_bufstatus => tx_bufstatus(1 downto 0),
211  rx_realign => rx_realign(0),
212  rx_disperr => rx_disperr_int(0),
213  crc_error => crc_error(0)
214 
215  );
216 
217  MGT_GT1 : entity work.gt_information
218  generic map (addr_width => 3)
219  port map(
220  ipb_clk => ipb_clk,
221  clk280 => clk280(1),
222  ipb_rst => ipb_rst,
223  reset => cntr_reset,
224  ipb_in => ipbw(N_SLV_GT1),
225  ipb_out => ipbr(N_SLV_GT1),
226  tx_pd => tx_pd(1),
227  rx_pd => rx_pd(1),
228  bc_cntr => bc_cntr_1,
229  bc_mux_cntr => bc_mux_cntr_1,
230  delay_cntr => delay_cntr_1,
231  not_intable => encode_error_int(1),
232  rx_resetdone => rx_resetdone(1),
233  rx_fsm_resetdone => rx_fsm_resetdone(1),
234  rx_byteisaligned => rx_byteisaligned(1),
235  tx_resetdone => tx_resetdone(1),
236  tx_fsm_resetdone => tx_fsm_resetdone(1),
237  tx_bufstatus => tx_bufstatus(3 downto 2),
238  rx_realign => rx_realign(1),
239  rx_disperr => rx_disperr_int(1),
240  crc_error => crc_error(1)
241  );
242 
243  MGT_GT2 : entity work.gt_information
244  generic map (addr_width => 3)
245  port map(
246  ipb_clk => ipb_clk,
247  clk280 => clk280(2),
248  ipb_rst => ipb_rst,
249  reset => cntr_reset,
250  ipb_in => ipbw(N_SLV_GT2),
251  ipb_out => ipbr(N_SLV_GT2),
252  tx_pd => tx_pd(2),
253  rx_pd => rx_pd(2),
254  bc_cntr => bc_cntr_2,
255  bc_mux_cntr => bc_mux_cntr_2,
256  delay_cntr => delay_cntr_2,
257  not_intable => encode_error_int(2),
258  rx_resetdone => rx_resetdone(2),
259  rx_fsm_resetdone => rx_fsm_resetdone(2),
260  rx_byteisaligned => rx_byteisaligned(2),
261  tx_resetdone => tx_resetdone(2),
262  tx_fsm_resetdone => tx_fsm_resetdone(2),
263  tx_bufstatus => tx_bufstatus(5 downto 4),
264  rx_realign => rx_realign(2),
265  rx_disperr => rx_disperr_int(2),
266  crc_error => '0'
267 
268  );
269 
270  MGT_GT3 : entity work.gt_information
271  generic map (addr_width => 3)
272  port map(
273  ipb_clk => ipb_clk,
274  clk280 => clk280(3),
275  ipb_rst => ipb_rst,
276  reset => cntr_reset,
277  ipb_in => ipbw(N_SLV_GT3),
278  ipb_out => ipbr(N_SLV_GT3),
279  tx_pd => tx_pd(3),
280  rx_pd => rx_pd(3),
281  bc_cntr => bc_cntr_3,
282  bc_mux_cntr => bc_mux_cntr_3,
283  delay_cntr => delay_cntr_3,
284  not_intable => encode_error_int(3),
285  rx_resetdone => rx_resetdone(3),
286  rx_fsm_resetdone => rx_fsm_resetdone(3),
287  rx_byteisaligned => rx_byteisaligned(3),
288  tx_resetdone => tx_resetdone(3),
289  tx_fsm_resetdone => tx_fsm_resetdone(3),
290  tx_bufstatus => tx_bufstatus(7 downto 6),
291  rx_realign => rx_realign(3),
292  rx_disperr => rx_disperr_int(3),
293  crc_error => '0'
294 
295  );
296 
297 end Behavioral;
cntrl_mgt_quad_slaves.Behavioral
MGT quad ipbus control.
Definition: cntrl_mgt_quad_slaves.vhd:63
cntrl_mgt_quad_slaves
MGT quad ipbus control.
Definition: cntrl_mgt_quad_slaves.vhd:16
gt_information
Definition: gt_information.vhd:19
gt_information.reset
in reset std_logic
reset
Definition: gt_information.vhd:27
gt_information.rx_realign
in rx_realign std_logic
rx realign status
Definition: gt_information.vhd:59
gt_information.ipb_rst
in ipb_rst std_logic
ipbus reset
Definition: gt_information.vhd:29
gt_information.rx_resetdone
in rx_resetdone std_logic
rx reset done of the gt if high is done
Definition: gt_information.vhd:47
gt_information.bc_mux_cntr
in bc_mux_cntr std_logic_vector( 4 downto 0)
bc value after the mux
Definition: gt_information.vhd:37
gt_information.rx_byteisaligned
in rx_byteisaligned std_logic
rx byte alignment
Definition: gt_information.vhd:51
gt_information.rx_disperr
in rx_disperr std_logic
rx disperr error
Definition: gt_information.vhd:61
gt_information.rx_pd
in rx_pd std_logic
power control for rx side of the gt
Definition: gt_information.vhd:45
gt_information.tx_resetdone
in tx_resetdone std_logic
tx reset done of the gt if high is done
Definition: gt_information.vhd:53
gt_information.not_intable
in not_intable std_logic
not in the table
Definition: gt_information.vhd:41
gt_information.clk280
in clk280 std_logic
fabric clock 280MHz
Definition: gt_information.vhd:25
gt_information.ipb_clk
in ipb_clk std_logic
ipbus clock
Definition: gt_information.vhd:23
gt_information.rx_fsm_resetdone
in rx_fsm_resetdone std_logic
rx fsm reset done of the if high is done
Definition: gt_information.vhd:49
gt_information.ipb_out
out ipb_out ipb_rbus
IPBus output bus going from slaves to master.
Definition: gt_information.vhd:33
gt_information.tx_fsm_resetdone
in tx_fsm_resetdone std_logic
tx fsm reset done of the gt if high is done
Definition: gt_information.vhd:55
gt_information.tx_bufstatus
in tx_bufstatus std_logic_vector( 1 downto 0)
tx buffer status
Definition: gt_information.vhd:57
gt_information.tx_pd
in tx_pd std_logic
power control for tx side of the gt
Definition: gt_information.vhd:43
gt_information.ipb_in
in ipb_in ipb_wbus
IPBus input bus going from master to slaves.
Definition: gt_information.vhd:31
gt_information.bc_cntr
in bc_cntr std_logic_vector( 4 downto 0)
bc cntr value
Definition: gt_information.vhd:35
gt_information.crc_error
in crc_error std_logic
crc_error
Definition: gt_information.vhd:64
gt_information.delay_cntr
in delay_cntr std_logic_vector( 3 downto 0)
first stage delay count of gt
Definition: gt_information.vhd:39
ipbus_decode_efex_cntrl_mgt_quad
Definition: ipbus_decode_efex_cntrl_mgt_quad.vhd:14
led_stretch
led stretch
Definition: led_stretch.vhd:12
led_stretch.clk
in clk std_logic
clock
Definition: led_stretch.vhd:17
led_stretch.input
in input std_logic
input
Definition: led_stretch.vhd:15
led_stretch.output
out output std_logic
output
Definition: led_stretch.vhd:20
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