ufc_controller Entity Reference

UFC_block... More...

Inheritance diagram for ufc_controller:

Entities
RTL	architecture
	UFC_block... More...

Libraries
IEEE
	Use standard library.

Use Clauses
STD_LOGIC_1164
NUMERIC_STD

Generics
TX_DATA_WIDTH	integer := 64
GAP_WIDTH	integer := 11

Ports
clock	in	STD_LOGIC
reset	in	STD_LOGIC
enable	in	STD_LOGIC
busy_tob	in	STD_LOGIC_VECTOR ( 3 DOWNTO 0 )
busy_raw	in	STD_LOGIC_VECTOR ( 3 DOWNTO 0 )
s_axi_tx_tready	in	STD_LOGIC
s_axi_ufc_tx_tready	in	STD_LOGIC
s_axi_ufc_tx_tvalid	out	STD_LOGIC
s_axi_ufc_tx_tdata	out	STD_LOGIC_VECTOR ( 2 DOWNTO 0 )
AXI_UFC_TDATA	out	STD_LOGIC_VECTOR ( ( TX_DATA_WIDTH- 1 ) DOWNTO 0 )

Detailed Description

UFC_block...

Create BUSY UFC message for output to Aurora Send when change in state of BUSY signals from Processors or when timer expires Heavily based on Ed's test bench module of the same name!

Author

David Sankey

Definition at line 16 of file ufc_controller.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/aurora/ufc_controller.vhd