ufc_controller.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity ufc_controller is
    generic (
           TX_DATA_WIDTH          : integer :=   64;
           GAP_WIDTH      : integer   :=   11       -- width of gap counter ex; 5 makes gap of 32 cycles
          );
    Port (
          clock                 : in STD_LOGIC;
          reset                 : in STD_LOGIC;
          enable                : in STD_LOGIC;
          busy_tob              : in STD_LOGIC_VECTOR(3 DOWNTO 0);
          busy_raw              : in STD_LOGIC_VECTOR(3 DOWNTO 0);
          s_axi_tx_tready       : in STD_LOGIC;
          s_axi_ufc_tx_tready   : in STD_LOGIC;
          s_axi_ufc_tx_tvalid   : out  STD_LOGIC;
          s_axi_ufc_tx_tdata    : out  STD_LOGIC_VECTOR(2 DOWNTO 0);
          AXI_UFC_TDATA         : out  STD_LOGIC_VECTOR((TX_DATA_WIDTH-1) DOWNTO 0)
         );
end ufc_controller;
 
architecture RTL of ufc_controller is
 
    signal gap_limit : unsigned(GAP_WIDTH-1 DOWNTO 0);
    signal gap_count : unsigned(GAP_WIDTH-1 DOWNTO 0);
    signal s_axi_ufc_tx_tvalid_i, enable_reg, reset_reg : std_logic :='0';
    signal message   : STD_LOGIC_VECTOR(7 DOWNTO 0);
    signal busy_tob_reg, busy_tob_last, busy_raw_reg, busy_raw_last : STD_LOGIC_VECTOR(3 DOWNTO 0);
    signal state     : std_logic_vector(1 downto 0)  := "00";
    signal send_message : std_logic :='0';
 
    attribute ASYNC_REG                   : string;
    attribute ASYNC_REG of busy_tob_reg : signal is "TRUE";
    attribute ASYNC_REG of busy_raw_reg : signal is "TRUE";
    attribute ASYNC_REG of busy_tob_last : signal is "TRUE";
    attribute ASYNC_REG of busy_raw_last : signal is "TRUE";
 
begin
gap_limit <= (others => '1');
 
register_reg_block: process (clock) begin
  if rising_edge (clock) then
    busy_tob_reg <= busy_tob;
    busy_raw_reg <= busy_raw;
  end if;
end process register_reg_block;
 
register_last_block: process (clock) begin
  if rising_edge (clock) then
    busy_tob_last <= busy_tob_reg;
    busy_raw_last <= busy_raw_reg;
  end if;
end process register_last_block;
 
control_reg_block: process (clock) begin
  if rising_edge (clock) then
    enable_reg <= enable;
    reset_reg <= reset;
  end if;
end process control_reg_block;
 
s_axi_ufc_tx_tdata <= "000"; -- 2 byte message
 
gap_counter: process (clock) begin
  if rising_edge (clock) then
    if (reset_reg = '1') or (state = "10") then
      gap_count <= (others => '0');
    elsif (gap_count /= gap_limit) then
      gap_count <= gap_count+1;
    else
      gap_count <= gap_count;
    end if;
  end if;
end process gap_counter;
 
time_to_send: process (clock) begin
  if rising_edge (clock) then
    if (reset_reg = '1') or (state = "10") then
      send_message <= '0';
    elsif (gap_count = gap_limit) or (busy_tob_reg /= busy_tob_last) or (busy_raw_reg /= busy_raw_last) then
      send_message <= '1';
    end if;
  end if;
end process time_to_send;
 
send_ufc: process (clock) begin
  if rising_edge (clock) then
    if (reset_reg = '1') or (enable_reg = '0') then
      s_axi_ufc_tx_tvalid_i <= '0';
      state <= "00";
    elsif (send_message = '1') and (s_axi_tx_tready = '1') and (s_axi_ufc_tx_tready = '0') and ((state = "00") or (state = "01")) then
      s_axi_ufc_tx_tvalid_i <= '1';   --begin arbitration
      state <= "01";
    elsif (send_message = '1') and (s_axi_ufc_tx_tvalid_i = '1') and (s_axi_ufc_tx_tready = '1') and (state = "01") then
      s_axi_ufc_tx_tvalid_i <= '0';  --arbitration complete
      state <= "10";
    elsif (state = "10") then
      state <= "00";
    else
      s_axi_ufc_tx_tvalid_i <= '0';  --error
    end if;
  end if;
end process send_ufc;
 
s_axi_ufc_tx_tvalid <= s_axi_ufc_tx_tvalid_i;
 
UFC_Message: process (clock)
  variable busy_source: STD_LOGIC_VECTOR(3 DOWNTO 0);
  variable tob_busy, raw_busy, parity_low, parity_high: std_logic;
  Begin
  if rising_edge (clock) then
    if (busy_tob_last /= "0000") then
      tob_busy := '1';
    else
      tob_busy := '0';
    end if;
    if (busy_raw_last /= "0000") then
      raw_busy := '1';
    else
      raw_busy := '0';
    end if;
    busy_source := busy_tob_last or busy_raw_last;
    parity_low := not(busy_source(0) xor raw_busy xor tob_busy);
    parity_high := not(busy_source(3) xor busy_source(2) xor busy_source(1));
    message <= parity_high & busy_source(3 downto 1) & parity_low & busy_source(0) & raw_busy & tob_busy;
  end if;
end process UFC_Message;
 
AXI_UFC_TDATA(15 DOWNTO 0) <= message & message;
AXI_UFC_TDATA((TX_DATA_WIDTH-1) downto 16)  <= (others => '0');
 
end RTL;