RTL Architecture Reference

UFC_block... More...

Processes
register_reg_block	( clock )
register_last_block	( clock )
control_reg_block	( clock )
gap_counter	( clock )
time_to_send	( clock )
send_ufc	( clock )
UFC_Message	( clock )

Signals
gap_limit	unsigned ( GAP_WIDTH- 1 DOWNTO 0 )
gap_count	unsigned ( GAP_WIDTH- 1 DOWNTO 0 )
s_axi_ufc_tx_tvalid_i	std_logic := ' 0 '
enable_reg	std_logic := ' 0 '
reset_reg	std_logic := ' 0 '
message	STD_LOGIC_VECTOR ( 7 DOWNTO 0 )
busy_tob_reg	STD_LOGIC_VECTOR ( 3 DOWNTO 0 )
busy_tob_last	STD_LOGIC_VECTOR ( 3 DOWNTO 0 )
busy_raw_reg	STD_LOGIC_VECTOR ( 3 DOWNTO 0 )
busy_raw_last	STD_LOGIC_VECTOR ( 3 DOWNTO 0 )
state	std_logic_vector ( 1 downto 0 ) := " 00 "
send_message	std_logic := ' 0 '

Attributes
ASYNC_REG	string
ASYNC_REG	signal is " TRUE "

Detailed Description

UFC_block...

Create BUSY UFC message for output to Aurora Send when change in state of BUSY signals from Processors or when timer expires Heavily based on Ed's test bench module of the same name!

Author

David Sankey

Definition at line 36 of file ufc_controller.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/aurora/ufc_controller.vhd