top_mgt_cfpga Entity Reference

Top MGT cFPGA. More...

Inheritance diagram for top_mgt_cfpga:

Entities
Behavioral	architecture

Libraries
IEEE
ipbus_lib
infrastructure_lib

Use Clauses
STD_LOGIC_1164
NUMERIC_STD
ipbus
all
mgt_type	Package <mgt_type>
packet_mux_type	Package <packet_mux_type>
ipbus_decode_efex_cntrl_mgt	Package <ipbus_decode_efex_cntrl_mgt>

Generics
NProcessorFPGA	positive := 4

Ports
start	in	std_logic
		start
clk40	in	std_logic
		clk40 generatred from ttc clock
clk160	in	std_logic
		clk160 generatred from ttc clock
rx_clk280	out	std_logic_vector ( 7 downto 0 )
		rx clock 280MHz
rx_clk160	out	std_logic_vector ( 3 downto 0 )
		rx clock 160MHz
Q_CLK_GTREFCLK_PAD_N_IN	in	std_logic_vector ( 2 downto 0 )
		clock input to the quad
Q_CLK_GTREFCLK_PAD_P_IN	in	std_logic_vector ( 2 downto 0 )
RXN_IN	in	std_logic_vector ( 11 downto 0 )
		rx quad input
RXP_IN	in	std_logic_vector ( 11 downto 0 )
TXN_OUT	out	std_logic_vector ( 11 downto 0 )
		tx quad input
TXP_OUT	out	std_logic_vector ( 11 downto 0 )
rx_resetdone	out	std_logic_vector ( 11 downto 0 )
		rx reset done of the all of the MGTs
rx_fsm_resetdone	out	std_logic_vector ( 11 downto 0 )
		rx fsm reset done of the all of the MGTs
rx_byteisaligned	out	std_logic_vector ( 11 downto 0 )
		rx_byteisaligned of the all of the MGTs
tx_resetdone	out	std_logic_vector ( 11 downto 0 )
		tx reset done of the all of the MGTs
tx_fsm_resetdone	out	std_logic_vector ( 11 downto 0 )
		tx fsm reset done of the all of the MGTs
tx_bufstatus	out	std_logic_vector ( 23 downto 0 )
		tx_bufstatus of the all of the MGTs
rx_realign	out	std_logic_vector ( 11 downto 0 )
		rx_realign of the all of the MGTs
rx_disperr	out	std_logic_vector ( 47 downto 0 )
		rx_disperr of the all of the MGTs
encode_error	out	std_logic_vector ( 47 downto 0 )
		encode_error of the all of the MGTs
mgt_commadret	out	std_logic_vector ( 1 downto 0 )
		mgt_commadret
loopback	in	std_logic_vector ( 5 downto 0 )
		loopback
mgt_SOFT_RESET_TX_IN	in	std_logic_vector ( 2 downto 0 )
		soft reset of tx quad
mgt_SOFT_RESET_RX_IN	in	std_logic_vector ( 2 downto 0 )
		soft reset of rx quad
mgt_QPLLLOCK_OUT	out	std_logic_vector ( 2 downto 0 )
		mgt_QPLLLOCK_OUT
mgt_QPLLREFCLKLOST_OUT	out	std_logic_vector ( 2 downto 0 )
		mgt_QPLLREFCLKLOST_OUT
data_from_mgt_bus	out	mgt_data_array ( NProcessorFPGA* 2 - 1 downto 0 )
		rx data from process fpgas
char_is_k_bus	out	std_logic_vector ( NProcessorFPGA* 2 - 1 downto 0 )
		k char from process fpgas
error_from_mgt_bus	out	std_logic_vector ( NProcessorFPGA* 2 - 1 downto 0 )
		error from the MGT links of 11.2Gbps
hub1_rx_data	out	std_logic_vector ( 31 downto 0 )
		rx data from ttc information gt0
hub2_rx_data	out	std_logic_vector ( 31 downto 0 )
		rx data from gt1

Detailed Description

Top MGT cFPGA.

This module performs the following functions:

• It combines together the MGT_quad_gen that generates single mgt quad of 6.4Gbps and mgt11g2_tx_rx_cfpga_gen that generate two mgt quads of 11.2Gbps.
• It creates ports for mgt data,k char and link errors from the process (11.2Gbps)
• It creates ports for mgt data ,k char and link errors from TTC information MGT(6.4Gbps)
• It powers down to unused MGTs

  Author

  Mohammed Siyad

Definition at line 23 of file top_mgt_cfpga.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd