eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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top_mgt_cfpga.vhd
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1 
10 
11 library IEEE;
12 use IEEE.STD_LOGIC_1164.all;
13 use IEEE.NUMERIC_STD.all;
14 library ipbus_lib;
15 use ipbus_lib.ipbus.all;
16 library infrastructure_lib;
17 use infrastructure_lib.all;
18 use infrastructure_lib.mgt_type.all;
19 use infrastructure_lib.packet_mux_type.all;
20 use infrastructure_lib.ipbus_decode_efex_cntrl_mgt.all;
22 
23 entity top_mgt_cfpga is
24  generic(
25  NProcessorFPGA : positive := 4 -- first TOB then Input Data for each FPGA in turn
26  );
27  port (
29  start : in std_logic;
31  clk40 : in std_logic;
33  clk160 : in std_logic;
35  rx_clk280 : out std_logic_vector(7 downto 0);
37  rx_clk160 : out std_logic_vector(3 downto 0); --11
39  Q_CLK_GTREFCLK_PAD_N_IN : in std_logic_vector(2 downto 0); --2
40  Q_CLK_GTREFCLK_PAD_P_IN : in std_logic_vector(2 downto 0); --2
42  RXN_IN : in std_logic_vector(11 downto 0); --11
43  RXP_IN : in std_logic_vector(11 downto 0); --11
45  TXN_OUT : out std_logic_vector(11 downto 0); --7
46  TXP_OUT : out std_logic_vector(11 downto 0); --7
48  rx_resetdone : out std_logic_vector(11 downto 0); --11
50  rx_fsm_resetdone : out std_logic_vector(11 downto 0); --11
52  rx_byteisaligned : out std_logic_vector(11 downto 0); --11
54  tx_resetdone : out std_logic_vector(11 downto 0); --11
56  tx_fsm_resetdone : out std_logic_vector(11 downto 0); --11
58  tx_bufstatus : out std_logic_vector (23 downto 0); --23
60  rx_realign : out std_logic_vector (11 downto 0); --11
62  rx_disperr : out std_logic_vector (47 downto 0); --47 -- rx_disperr for debug
64  encode_error : out std_logic_vector (47 downto 0); --47 --- 10/8 encoder for debug
66  mgt_commadret : out std_logic_vector(1 downto 0); --9 (just for incoming Hub data...)
68  loopback : in std_logic_vector(5 downto 0); --5
70  mgt_SOFT_RESET_TX_IN : in std_logic_vector(2 downto 0); --2
72  mgt_SOFT_RESET_RX_IN : in std_logic_vector(2 downto 0); --2
74  mgt_QPLLLOCK_OUT : out std_logic_vector(2 downto 0);
76  mgt_QPLLREFCLKLOST_OUT : out std_logic_vector(2 downto 0);
78  data_from_mgt_bus : out mgt_data_array(NProcessorFPGA*2 - 1 downto 0); -- first TOB then Input Data for each FPGA in turn
80  char_is_k_bus : out std_logic_vector(NProcessorFPGA*2 - 1 downto 0); -- first TOB then Input Data for each FPGA in turn
82  error_from_mgt_bus : out std_logic_vector(NProcessorFPGA*2 - 1 downto 0); -- first TOB then Input Data for each FPGA in turn
84  hub1_rx_data : out std_logic_vector(31 downto 0); -- ttc information
86  hub2_rx_data : out std_logic_vector(31 downto 0) -- rod busy.
87  );
88 end top_mgt_cfpga;
89 
90 architecture Behavioral of top_mgt_cfpga is
91 
92  signal probe0 : std_logic_vector(67 downto 0);
93  signal gt_rxpd : mgt_rxpd_array(2 downto 0);
94  signal gt_txpd : mgt_txpd_array(2 downto 0);
95  signal mgt_DATA_VALID_IN : std_logic_vector(5 downto 0);
96  signal MGT_RXN_in, MGT_RXP_in : mgt_rx_array(2 downto 0);
97  signal MGT_TXN_in, MGT_TXP_in : mgt_tx_array(2 downto 0);
98  signal mgt_TXUSRCLK_OUT, mgt_RXUSRCLK_OUT, mgt_tx_fsm_resetdone, mgt_rx_fsm_resetdone, MGT_Commadet_int : std_logic_vector(11 downto 0);
99  signal mgt_QPLLREFCLKLOST_OUT_i, mgt_QPLLLOCK_OUT_i : std_logic_vector(1 downto 0);
100  signal rxdata_quad_array : mgt_rxdata_array (2 downto 0);
101  signal mgt_txdata : mgt_txdata_array(2 downto 0);
102  signal mgt_loopback_reg : std_logic_vector (14 downto 0);
103  signal mgt_txbufstatus : mgt_txbufstatus_array(2 downto 0);
104  signal mgt_rxcommadet : mgt_rxcommadet_array (2 downto 0);
105  signal mgt_rxbyterealign : mgt_rxbyterealign_array(2 downto 0);
106  signal mgt_rx_resetdone : mgt_rxresetdone_array (2 downto 0);
107  signal mgt_rxbyteisaligned : mgt_rxbyteisaligned_array (2 downto 0);
108  signal mgt_tx_resetdone : mgt_txresetdone_array (2 downto 0);
109  signal mgt_txcharisk : mgt_txcharisk_array (2 downto 0);
110  signal mgt_loopback_in : mgt_loopback_array (2 downto 0);
111  signal mgt_rxchariscomma : mgt_rxchariskcomm_array(2 downto 0);
112  signal mgt_rxcharisk : mgt_rxcharisk_array(2 downto 0);
113  signal mgt_rxdisperr : mgt_rxdisperr_array(11 downto 0);
114  signal mgt_rxnotintable : mgt_rxnotintable_array(11 downto 0);
115  signal rxbyteisaligned : std_logic_vector(11 downto 0);
116  signal mgt_rxcharisk_reg, txcharisk : std_logic_vector(47 downto 0);
117  signal reset : std_logic;
118  signal rx_resetdone_i : std_logic_vector(11 downto 0); --11
119  signal rx_disperr_i, encode_error_i : std_logic_vector (47 downto 0);
120  signal gt0_cpllfbclklost_out, gt0_cplllock_out : std_logic_vector(0 downto 0);
121  signal gt1_cpllfbclklost_out, gt1_cplllock_out : std_logic_vector(0 downto 0);
122  signal gt2_cpllfbclklost_out, gt2_cplllock_out : std_logic_vector(0 downto 0);
123  signal gt3_cpllfbclklost_out, gt3_cplllock_out : std_logic_vector(0 downto 0);
124 
125 begin
126 
127  rx_disperr <= rx_disperr_i;
128  encode_error <= encode_error_i;
129 
130 
131  rx_resetdone <= rx_resetdone_i(11 downto 0);
132  rx_byteisaligned <= rxbyteisaligned ;
133  rx_fsm_resetdone <= mgt_rx_fsm_resetdone;
134  tx_fsm_resetdone <= mgt_tx_fsm_resetdone;
135 
136 
137  reset <= '0';
138 
139  mgt_QPLLLOCK_OUT <= gt0_cplllock_out (0) & mgt_QPLLLOCK_OUT_i;
140  mgt_QPLLREFCLKLOST_OUT <= gt0_cpllfbclklost_out(0) & mgt_QPLLREFCLKLOST_OUT_i;
141 
142 
143  rx_pwr_on_gen : for i in 0 to 2 --loop --0 to 2
144 
145 
146 
147  generate
148  gt_rxpd(i).gt0_rxpd <= "00";
149  gt_rxpd(i).gt1_rxpd <= "00";
150  gt_rxpd(i).gt2_rxpd <= "00";
151  gt_rxpd(i).gt3_rxpd <= "00";
152  gt_txpd(i).gt0_txpd <= "11";
153  gt_txpd(i).gt1_txpd <= "11";
154  gt_txpd(i).gt2_txpd <= "11";
155  gt_txpd(i).gt3_txpd <= "11";
156  end generate;
157 
158 -- gt_rxpd(0).gt0_rxpd <= "00";
159 -- gt_rxpd(0).gt1_rxpd <= "00";
160 -- gt_rxpd(0).gt2_rxpd <= "00";
161 -- gt_rxpd(0).gt3_rxpd <= "00";
162 
163 -- gt_txpd(0).gt0_txpd <= "11";
164 -- gt_txpd(0).gt1_txpd <= "11";
165 -- gt_txpd(0).gt2_txpd <= "11";
166 -- gt_txpd(0).gt3_txpd <= "11";
167 
168 
169 
170 
171  -----------------------------------
172  --rx_clk160 <= mgt_RXUSRCLK_OUT(3 downto 0);
173  rx_clk160 <= mgt_RXUSRCLK_OUT(11 downto 8);
174  rx_clk280 <= mgt_RXUSRCLK_OUT(7 downto 0);
175 
176 -- assign rx data
177  Processor_1_TOB : process(mgt_RXUSRCLK_OUT(0))
178  begin
179  if rising_edge(mgt_RXUSRCLK_OUT(0)) then
180  data_from_mgt_bus(0) <= rxdata_quad_array(0).gt0_rxdata_out;
181  char_is_k_bus(0) <= mgt_rxcharisk(0).gt0_rxcharisk_out(0);
182  if (mgt_rxdisperr(0).gt0_rxdisperr = "0000") and (mgt_rxnotintable(0).gt0_rxnotintable = "0000") then
183  error_from_mgt_bus(0) <= '0';
184  else
185  error_from_mgt_bus(0) <= '1';
186  end if;
187  end if;
188  end process Processor_1_TOB;
189 
190  Processor_1_Raw : process(mgt_RXUSRCLK_OUT(1))
191  begin
192  if rising_edge(mgt_RXUSRCLK_OUT(1)) then
193  data_from_mgt_bus(1) <= rxdata_quad_array(0).gt1_rxdata_out;
194  char_is_k_bus(1) <= mgt_rxcharisk(0).gt1_rxcharisk_out(0);
195  if (mgt_rxdisperr(0).gt1_rxdisperr = "0000") and (mgt_rxnotintable(0).gt1_rxnotintable = "0000") then
196  error_from_mgt_bus(1) <= '0';
197  else
198  error_from_mgt_bus(1) <= '1';
199  end if;
200  end if;
201  end process Processor_1_Raw;
202 
203  Processor_2_TOB : process(mgt_RXUSRCLK_OUT(2))
204  begin
205  if rising_edge(mgt_RXUSRCLK_OUT(2)) then
206  data_from_mgt_bus(2) <= rxdata_quad_array(0).gt2_rxdata_out;
207  char_is_k_bus(2) <= mgt_rxcharisk(0).gt2_rxcharisk_out(0);
208  if (mgt_rxdisperr(0).gt2_rxdisperr = "0000") and (mgt_rxnotintable(0).gt2_rxnotintable = "0000") then
209  error_from_mgt_bus(2) <= '0';
210  else
211  error_from_mgt_bus(2) <= '1';
212  end if;
213  end if;
214  end process Processor_2_TOB;
215 
216  Processor_2_Raw : process(mgt_RXUSRCLK_OUT(3))
217  begin
218  if rising_edge(mgt_RXUSRCLK_OUT(3)) then
219  data_from_mgt_bus(3) <= rxdata_quad_array(0).gt3_rxdata_out;
220  char_is_k_bus(3) <= mgt_rxcharisk(0).gt3_rxcharisk_out(0);
221  if (mgt_rxdisperr(0).gt3_rxdisperr = "0000") and (mgt_rxnotintable(0).gt3_rxnotintable = "0000") then
222  error_from_mgt_bus(3) <= '0';
223  else
224  error_from_mgt_bus(3) <= '1';
225  end if;
226  end if;
227  end process Processor_2_Raw;
228 
229 
230  Processor_3_TOB : process(mgt_RXUSRCLK_OUT(4))
231  begin
232  if rising_edge(mgt_RXUSRCLK_OUT(4)) then
233  data_from_mgt_bus(4) <= rxdata_quad_array(1).gt0_rxdata_out;
234  char_is_k_bus(4) <= mgt_rxcharisk(1).gt0_rxcharisk_out(0);
235  if (mgt_rxdisperr(1).gt0_rxdisperr = "0000") and (mgt_rxnotintable(1).gt0_rxnotintable = "0000") then
236  error_from_mgt_bus(4) <= '0';
237  else
238  error_from_mgt_bus(4) <= '1';
239  end if;
240  end if;
241  end process Processor_3_TOB;
242 
243  Processor_3_Raw : process(mgt_RXUSRCLK_OUT(5))
244  begin
245  if rising_edge(mgt_RXUSRCLK_OUT(5)) then
246  data_from_mgt_bus(5) <= rxdata_quad_array(1).gt1_rxdata_out;
247  char_is_k_bus(5) <= mgt_rxcharisk(1).gt1_rxcharisk_out(0);
248  if (mgt_rxdisperr(1).gt1_rxdisperr = "0000") and (mgt_rxnotintable(1).gt1_rxnotintable = "0000") then
249  error_from_mgt_bus(5) <= '0';
250  else
251  error_from_mgt_bus(5) <= '1';
252  end if;
253  end if;
254  end process Processor_3_Raw;
255 
256 
257  Processor_4_TOB : process(mgt_RXUSRCLK_OUT(6))
258  begin
259  if rising_edge(mgt_RXUSRCLK_OUT(6)) then
260  data_from_mgt_bus(6) <= rxdata_quad_array(1).gt2_rxdata_out;
261  char_is_k_bus(6) <= mgt_rxcharisk(1).gt2_rxcharisk_out(0);
262  if (mgt_rxdisperr(1).gt2_rxdisperr = "0000") and (mgt_rxnotintable(1).gt2_rxnotintable = "0000") then
263  error_from_mgt_bus(6) <= '0';
264  else
265  error_from_mgt_bus(6) <= '1';
266  end if;
267  end if;
268  end process Processor_4_TOB;
269 
270  Processor_4_Raw : process(mgt_RXUSRCLK_OUT(7))
271  begin
272  if rising_edge(mgt_RXUSRCLK_OUT(7)) then
273  data_from_mgt_bus(7) <= rxdata_quad_array(1).gt3_rxdata_out;
274  char_is_k_bus(7) <= mgt_rxcharisk(1).gt3_rxcharisk_out(0);
275  if (mgt_rxdisperr(1).gt3_rxdisperr = "0000") and (mgt_rxnotintable(1).gt3_rxnotintable = "0000") then
276  error_from_mgt_bus(7) <= '0';
277  else
278  error_from_mgt_bus(7) <= '1';
279  end if;
280  end if;
281  end process Processor_4_Raw;
282 
283 
284 
285 
286  hub1_rx_data <= rxdata_quad_array(2).gt0_rxdata_out; --2
287  hub2_rx_data <= rxdata_quad_array(2).gt1_rxdata_out; --2
288  mgt_commadret <= MGT_Commadet_int(9 downto 8);
289 
290  --------------------------------------------------------
291 
292  --mgt for receiving topo and raw data from the processing fpga1,fpga2,fpga3 and fpga4
293 
294  MGT_TX_RX_6G4 : entity infrastructure_lib.MGT_quad_gen
295  generic map (num_quad_tx_rx => 1)
296  port map (
297  ---refclk160 => clk160,
298  TTC_CLK => clk40,
299  MGT_CLK_GTREFCLK_PAD_N_IN => Q_CLK_GTREFCLK_PAD_N_IN (2 downto 2), --2
300  MGT_CLK_GTREFCLK_PAD_P_IN => Q_CLK_GTREFCLK_PAD_P_IN (2 downto 2), --2
301  mgt_TXUSRCLK_OUT => mgt_TXUSRCLK_OUT(11 downto 8), --11
302  mgt_RXUSRCLK_OUT => mgt_RXUSRCLK_OUT(11 downto 8), --11
303  mgt_SOFT_RESET_TX_IN => mgt_SOFT_RESET_TX_IN(2 downto 2), --2
304  mgt_SOFT_RESET_RX_IN => mgt_SOFT_RESET_RX_IN(2 downto 2), --2
305  -- data
306  RXN_IN => MGT_RXN_IN(2 downto 2), --2
307  RXP_IN => MGT_RXP_IN(2 downto 2), --2
308  TXN_IN => MGT_TXN_IN(2 downto 2), --2
309  TXP_IN => MGT_TXP_IN(2 downto 2), --2
310  rxdata_quad_array => rxdata_quad_array (2 downto 2), --2
311  txdata_quad_array => mgt_txdata(2 downto 2), --2
312  -- status and monitoring => --2
313  gt_rxpd_array => gt_rxpd (2 downto 2), --2
314  gt_txpd_array => gt_txpd (2 downto 2),
315  mgt_TX_FSM_RESET_DONE => mgt_tx_fsm_resetdone(11 downto 8), --11
316  mgt_RX_FSM_RESET_DONE => mgt_rx_fsm_resetdone(11 downto 8), --11
317  rxbyteisaligned_quad_array => mgt_rxbyteisaligned (2 downto 2), --2
318  rxresetdone_quad_array => mgt_rx_resetdone (2 downto 2), --2
319  txresetdone_quad_array => mgt_tx_resetdone (2 downto 2), --2
320  loopback_quad_array => mgt_loopback_in (2 downto 2), --2
321  rxchariscomma_quad_array => mgt_rxchariscomma (2 downto 2), --2
322  rxcharisk_quad_array => mgt_rxcharisk (2 downto 2), --2
323  txcharisk_quad_array => mgt_txcharisk (2 downto 2), --2
324  txbufstatus_quad_array => mgt_txbufstatus (2 downto 2), --2
325  rxbyterealign_quad_array => mgt_rxbyterealign (2 downto 2), --2
326  rxcommadet_quad_array => mgt_rxcommadet (2 downto 2), --2
327  rxdisperr_quad_array => mgt_rxdisperr (2 downto 2), --2
328  rxnotintable_quad_array => mgt_rxnotintable (2 downto 2), --2
329  -- mgt_QPLLREFCLKLOST_OUT => mgt_QPLLREFCLKLOST_OUT (0 downto 0),
330  -- mgt_QPLLLOCK_OUT => mgt_QPLLLOCK_OUT(0 downto 0),
331  gt0_cpllfbclklost_out => gt0_cpllfbclklost_out (0 downto 0),
332  gt0_cplllock_out => gt0_cplllock_out (0 downto 0),
333  gt1_cpllfbclklost_out => gt1_cpllfbclklost_out(0 downto 0),
334  gt1_cplllock_out => gt1_cplllock_out(0 downto 0),
335  gt2_cpllfbclklost_out => gt2_cpllfbclklost_out(0 downto 0),
336  gt2_cplllock_out => gt2_cplllock_out(0 downto 0),
337  gt3_cpllfbclklost_out => gt3_cpllfbclklost_out(0 downto 0),
338  gt3_cplllock_out => gt3_cplllock_out(0 downto 0)
339 
340  );
341 
342 
343  --------- mgt quad generate for 11.2 G
344 
345  MGT_TX_RX_11G2 : entity infrastructure_lib.mgt11g2_tx_rx_cfpga_gen
346 
347  generic map(num_quad_tx_rx => 2)
348 
349  port map (
350  TTC_CLK => clk40,
351  MGT_CLK_GTREFCLK_PAD_N_IN => Q_CLK_GTREFCLK_PAD_N_IN (1 downto 0),
352  MGT_CLK_GTREFCLK_PAD_P_IN => Q_CLK_GTREFCLK_PAD_P_IN (1 downto 0),
353  mgt_TXUSRCLK_OUT => mgt_TXUSRCLK_OUT(7 downto 0),
354  mgt_RXUSRCLK_OUT => mgt_RXUSRCLK_OUT(7 downto 0),
355  mgt_SOFT_RESET_TX_IN => mgt_SOFT_RESET_TX_IN(1 downto 0),
356  mgt_SOFT_RESET_RX_IN => mgt_SOFT_RESET_RX_IN(1 downto 0),
357  -- data
358  RXN_IN => MGT_RXN_IN(1 downto 0),
359  RXP_IN => MGT_RXP_IN(1 downto 0),
360  TXN_IN => MGT_TXN_IN(1 downto 0),
361  TXP_IN => MGT_TXP_IN(1 downto 0),
362  rxdata_quad_array => rxdata_quad_array (1 downto 0),
363  txdata_quad_array => mgt_txdata(1 downto 0),
364  -- status and monitoring =>
365  mgt_DATA_VALID_IN => "11111111",
366  gt_rxpd_array => gt_rxpd (1 downto 0),
367  gt_txpd_array => gt_txpd (1 downto 0),
368  mgt_TX_FSM_RESET_DONE => mgt_tx_fsm_resetdone(7 downto 0),
369  mgt_RX_FSM_RESET_DONE => mgt_rx_fsm_resetdone(7 downto 0),
370  rxbyteisaligned_quad_array => mgt_rxbyteisaligned (1 downto 0),
371  rxresetdone_quad_array => mgt_rx_resetdone (1 downto 0),
372  txresetdone_quad_array => mgt_tx_resetdone (1 downto 0),
373  -- loopback_quad_array => mgt_loopback_in (2 downto 1),
374  rxchariscomma_quad_array => mgt_rxchariscomma (1 downto 0),
375  rxcharisk_quad_array => mgt_rxcharisk (1 downto 0),
376  txcharisk_quad_array => mgt_txcharisk (1 downto 0),
377  txbufstatus_quad_array => mgt_txbufstatus (1 downto 0),
378  rxbyterealign_quad_array => mgt_rxbyterealign (1 downto 0),
379  rxcommadet_quad_array => mgt_rxcommadet (1 downto 0),
380  rxdisperr_quad_array => mgt_rxdisperr (1 downto 0),
381  rxnotintable_quad_array => mgt_rxnotintable (1 downto 0),
382  mgt_QPLLREFCLKLOST_OUT => mgt_QPLLREFCLKLOST_OUT_i (1 downto 0),
383  mgt_QPLLLOCK_OUT => mgt_QPLLLOCK_OUT_i(1 downto 0)
384 
385  );
386 
387 
388 
389  mgt_gen : for i in 0 to 2 --loop
390 
391  generate
392 
393  MGT_Commadet_int(i+3*i downto i+3*i) <= mgt_rxchariscomma(i).gt0_rxchariscomma_out(0 downto 0); -- asginment of the rxchriscomma
394  MGT_Commadet_int(i+1+3*i downto i+1+3*i) <= mgt_rxchariscomma(i).gt1_rxchariscomma_out(0 downto 0); -- asginment of the rxchriscomma
395  MGT_Commadet_int(i+2+3*i downto i+2+3*i) <= mgt_rxchariscomma(i).gt2_rxchariscomma_out(0 downto 0); -- asginment of the rxchriscomma
396  MGT_Commadet_int(i+3+3*i downto i+3+3*i) <= mgt_rxchariscomma(i).gt3_rxchariscomma_out(0 downto 0); -- asginment of the rxchriscomma
397 
398  rx_realign (i+3*i) <= mgt_rxbyterealign(i).gt0_rxbyterealign; -- asignment of rxbyterealign
399  rx_realign(i+1+3*i) <= mgt_rxbyterealign(i).gt1_rxbyterealign; -- asignment of rxbyterealign
400  rx_realign(i+2+3*i) <= mgt_rxbyterealign(i).gt2_rxbyterealign; -- asignment of rxbyterealign
401  rx_realign(i+3+3*i) <= mgt_rxbyterealign(i).gt3_rxbyterealign; -- asignment of rxbyterealign
402 
403  rx_resetdone_i (i+3*i) <= mgt_rx_resetdone(i).gt0_rxresetdone; -- asignment of rx_resetdone
404  rx_resetdone_i(i+1+3*i) <= mgt_rx_resetdone(i).gt1_rxresetdone; -- asignment of rx_resetdone
405  rx_resetdone_i(i+2+3*i) <= mgt_rx_resetdone(i).gt2_rxresetdone; -- asignment of rx_resetdone
406  rx_resetdone_i(i+3+3*i) <= mgt_rx_resetdone(i).gt3_rxresetdone; -- asignment of rx_resetdone
407 
408  tx_resetdone (i+3*i) <= mgt_tx_resetdone(i).gt0_txresetdone; -- asignment of tx_resetdone
409  tx_resetdone(i+1+3*i) <= mgt_tx_resetdone(i).gt1_txresetdone; -- asignment of tx_resetdone
410  tx_resetdone(i+2+3*i) <= mgt_tx_resetdone(i).gt2_txresetdone; -- asignment of tx_resetdone
411  tx_resetdone(i+3+3*i) <= mgt_tx_resetdone(i).gt3_txresetdone; -- asignment of tx_resetdone
412 
413 
414 
415 
416 
417  rxbyteisaligned (i+3*i) <= mgt_rxbyteisaligned(i).gt0_rxbyteisaligned;
418  rxbyteisaligned(i+1+3*i) <= mgt_rxbyteisaligned(i).gt1_rxbyteisaligned;
419  rxbyteisaligned(i+2+3*i) <= mgt_rxbyteisaligned(i).gt2_rxbyteisaligned;
420  rxbyteisaligned(i+3+3*i) <= mgt_rxbyteisaligned(i).gt3_rxbyteisaligned;
421 
422  mgt_rxcharisk_reg(i+3+15*i downto i+15*i) <= mgt_rxcharisk(i).gt0_rxcharisk_out;
423  mgt_rxcharisk_reg(i+7+15*i downto i+4+15*i) <= mgt_rxcharisk(i).gt1_rxcharisk_out;
424  mgt_rxcharisk_reg(i+11+15*i downto i+8+15*i) <= mgt_rxcharisk(i).gt2_rxcharisk_out;
425  mgt_rxcharisk_reg(i+15+15*i downto i+12+15*i) <= mgt_rxcharisk(i).gt3_rxcharisk_out;
426 
427 
428  rx_disperr_i(i+3+15*i downto i+15*i) <= mgt_rxdisperr(i).gt0_rxdisperr;
429  rx_disperr_i(i+7+15*i downto i+4+15*i) <= mgt_rxdisperr(i).gt1_rxdisperr;
430  rx_disperr_i(i+11+15*i downto i+8+15*i) <= mgt_rxdisperr(i).gt2_rxdisperr;
431  rx_disperr_i(i+15+15*i downto i+12+15*i) <= mgt_rxdisperr(i).gt3_rxdisperr;
432 
433  encode_error_i(i+3+15*i downto i+15*i) <= mgt_rxnotintable(i).gt0_rxnotintable; -- asignment of 10b/8b encoding error-
434  encode_error_i(i+7+15*i downto i+4+15*i) <= mgt_rxnotintable(i).gt1_rxnotintable; -- asignment of 10b/8b encoding error
435  encode_error_i(i+11+15*i downto i+8+15*i) <= mgt_rxnotintable(i).gt2_rxnotintable; -- asignment of 10b/8b encoding error
436  encode_error_i(i+15+15*i downto i+12+15*i) <= mgt_rxnotintable(i).gt3_rxnotintable; -- asignment of 10b/8b encoding error
437 
438  MGT_RXN_IN(i).RXN_IN <= RXN_IN(i+3+3*i downto i+3*i); -- rx input asignment
439  MGT_RXP_IN(i).RXP_IN <= RXP_IN(i+3+3*i downto i+3*i); -- rx input asignment
440 
441 
442  TXN_OUT(i+3+3*i downto i+3*i) <= MGT_TXN_IN(i).TXN_OUT;
443  TXP_OUT(i+3+3*i downto i+3*i) <= MGT_TXP_IN(i).TXP_OUT;
444 
445 
446  end generate mgt_gen;
447 
448 
449 
450 
451 
452 
453 end Behavioral;
MGT_quad_gen
MGT quad generation.
Definition: mgt_quad_gen.vhd:34
ipbus_decode_efex_cntrl_mgt
Definition: ipbus_decode_efex_cntrl_mgt.vhd:14
mgt11g2_tx_rx_cfpga_gen
MGT quad.
Definition: mgt11g2_tx_rx_cfgpa_gen.vhd:16
mgt_type
Definition: mgt_type_pkg.vhd:4
packet_mux_type
Definition: packet_mux_type.vhd:4
top_mgt_cfpga.Behavioral
Definition: top_mgt_cfpga.vhd:90
top_mgt_cfpga
Top MGT cFPGA.
Definition: top_mgt_cfpga.vhd:23
top_mgt_cfpga.hub1_rx_data
out hub1_rx_data std_logic_vector( 31 downto 0)
rx data from ttc information gt0
Definition: top_mgt_cfpga.vhd:84
top_mgt_cfpga.rx_resetdone
out rx_resetdone std_logic_vector( 11 downto 0)
rx reset done of the all of the MGTs
Definition: top_mgt_cfpga.vhd:48
top_mgt_cfpga.clk40
in clk40 std_logic
clk40 generatred from ttc clock
Definition: top_mgt_cfpga.vhd:31
top_mgt_cfpga.rx_disperr
out rx_disperr std_logic_vector( 47 downto 0)
rx_disperr of the all of the MGTs
Definition: top_mgt_cfpga.vhd:62
top_mgt_cfpga.rx_clk160
out rx_clk160 std_logic_vector( 3 downto 0)
rx clock 160MHz
Definition: top_mgt_cfpga.vhd:37
top_mgt_cfpga.tx_fsm_resetdone
out tx_fsm_resetdone std_logic_vector( 11 downto 0)
tx fsm reset done of the all of the MGTs
Definition: top_mgt_cfpga.vhd:56
top_mgt_cfpga.error_from_mgt_bus
out error_from_mgt_bus std_logic_vector( NProcessorFPGA* 2- 1 downto 0)
error from the MGT links of 11.2Gbps
Definition: top_mgt_cfpga.vhd:82
top_mgt_cfpga.rx_fsm_resetdone
out rx_fsm_resetdone std_logic_vector( 11 downto 0)
rx fsm reset done of the all of the MGTs
Definition: top_mgt_cfpga.vhd:50
top_mgt_cfpga.char_is_k_bus
out char_is_k_bus std_logic_vector( NProcessorFPGA* 2- 1 downto 0)
k char from process fpgas
Definition: top_mgt_cfpga.vhd:80
top_mgt_cfpga.encode_error
out encode_error std_logic_vector( 47 downto 0)
encode_error of the all of the MGTs
Definition: top_mgt_cfpga.vhd:64
top_mgt_cfpga.mgt_QPLLLOCK_OUT
out mgt_QPLLLOCK_OUT std_logic_vector( 2 downto 0)
mgt_QPLLLOCK_OUT
Definition: top_mgt_cfpga.vhd:74
top_mgt_cfpga.mgt_QPLLREFCLKLOST_OUT
out mgt_QPLLREFCLKLOST_OUT std_logic_vector( 2 downto 0)
mgt_QPLLREFCLKLOST_OUT
Definition: top_mgt_cfpga.vhd:76
top_mgt_cfpga.hub2_rx_data
out hub2_rx_data std_logic_vector( 31 downto 0)
rx data from gt1
Definition: top_mgt_cfpga.vhd:87
top_mgt_cfpga.clk160
in clk160 std_logic
clk160 generatred from ttc clock
Definition: top_mgt_cfpga.vhd:33
top_mgt_cfpga.tx_resetdone
out tx_resetdone std_logic_vector( 11 downto 0)
tx reset done of the all of the MGTs
Definition: top_mgt_cfpga.vhd:54
top_mgt_cfpga.loopback
in loopback std_logic_vector( 5 downto 0)
loopback
Definition: top_mgt_cfpga.vhd:68
top_mgt_cfpga.mgt_SOFT_RESET_TX_IN
in mgt_SOFT_RESET_TX_IN std_logic_vector( 2 downto 0)
soft reset of tx quad
Definition: top_mgt_cfpga.vhd:70
top_mgt_cfpga.Q_CLK_GTREFCLK_PAD_N_IN
in Q_CLK_GTREFCLK_PAD_N_IN std_logic_vector( 2 downto 0)
clock input to the quad
Definition: top_mgt_cfpga.vhd:39
top_mgt_cfpga.RXN_IN
in RXN_IN std_logic_vector( 11 downto 0)
rx quad input
Definition: top_mgt_cfpga.vhd:42
top_mgt_cfpga.mgt_SOFT_RESET_RX_IN
in mgt_SOFT_RESET_RX_IN std_logic_vector( 2 downto 0)
soft reset of rx quad
Definition: top_mgt_cfpga.vhd:72
top_mgt_cfpga.start
in start std_logic
start
Definition: top_mgt_cfpga.vhd:29
top_mgt_cfpga.rx_realign
out rx_realign std_logic_vector( 11 downto 0)
rx_realign of the all of the MGTs
Definition: top_mgt_cfpga.vhd:60
top_mgt_cfpga.data_from_mgt_bus
out data_from_mgt_bus mgt_data_array( NProcessorFPGA* 2- 1 downto 0)
rx data from process fpgas
Definition: top_mgt_cfpga.vhd:78
top_mgt_cfpga.rx_clk280
out rx_clk280 std_logic_vector( 7 downto 0)
rx clock 280MHz
Definition: top_mgt_cfpga.vhd:35
top_mgt_cfpga.TXN_OUT
out TXN_OUT std_logic_vector( 11 downto 0)
tx quad input
Definition: top_mgt_cfpga.vhd:45
top_mgt_cfpga.tx_bufstatus
out tx_bufstatus std_logic_vector( 23 downto 0)
tx_bufstatus of the all of the MGTs
Definition: top_mgt_cfpga.vhd:58
top_mgt_cfpga.mgt_commadret
out mgt_commadret std_logic_vector( 1 downto 0)
mgt_commadret
Definition: top_mgt_cfpga.vhd:66
top_mgt_cfpga.rx_byteisaligned
out rx_byteisaligned std_logic_vector( 11 downto 0)
rx_byteisaligned of the all of the MGTs
Definition: top_mgt_cfpga.vhd:52
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