Behavioral Architecture Reference

Processes
Processor_1_TOB	( mgt_RXUSRCLK_OUT( 0 ) )
Processor_1_Raw	( mgt_RXUSRCLK_OUT( 1 ) )
Processor_2_TOB	( mgt_RXUSRCLK_OUT( 2 ) )
Processor_2_Raw	( mgt_RXUSRCLK_OUT( 3 ) )
Processor_3_TOB	( mgt_RXUSRCLK_OUT( 4 ) )
Processor_3_Raw	( mgt_RXUSRCLK_OUT( 5 ) )
Processor_4_TOB	( mgt_RXUSRCLK_OUT( 6 ) )
Processor_4_Raw	( mgt_RXUSRCLK_OUT( 7 ) )

Signals
probe0	std_logic_vector ( 67 downto 0 )
gt_rxpd	mgt_rxpd_array ( 2 downto 0 )
gt_txpd	mgt_txpd_array ( 2 downto 0 )
mgt_DATA_VALID_IN	std_logic_vector ( 5 downto 0 )
MGT_RXN_in	mgt_rx_array ( 2 downto 0 )
MGT_RXP_in	mgt_rx_array ( 2 downto 0 )
MGT_TXN_in	mgt_tx_array ( 2 downto 0 )
MGT_TXP_in	mgt_tx_array ( 2 downto 0 )
mgt_TXUSRCLK_OUT	std_logic_vector ( 11 downto 0 )
mgt_RXUSRCLK_OUT	std_logic_vector ( 11 downto 0 )
mgt_tx_fsm_resetdone	std_logic_vector ( 11 downto 0 )
mgt_rx_fsm_resetdone	std_logic_vector ( 11 downto 0 )
MGT_Commadet_int	std_logic_vector ( 11 downto 0 )
mgt_QPLLREFCLKLOST_OUT_i	std_logic_vector ( 1 downto 0 )
mgt_QPLLLOCK_OUT_i	std_logic_vector ( 1 downto 0 )
rxdata_quad_array	mgt_rxdata_array ( 2 downto 0 )
mgt_txdata	mgt_txdata_array ( 2 downto 0 )
mgt_loopback_reg	std_logic_vector ( 14 downto 0 )
mgt_txbufstatus	mgt_txbufstatus_array ( 2 downto 0 )
mgt_rxcommadet	mgt_rxcommadet_array ( 2 downto 0 )
mgt_rxbyterealign	mgt_rxbyterealign_array ( 2 downto 0 )
mgt_rx_resetdone	mgt_rxresetdone_array ( 2 downto 0 )
mgt_rxbyteisaligned	mgt_rxbyteisaligned_array ( 2 downto 0 )
mgt_tx_resetdone	mgt_txresetdone_array ( 2 downto 0 )
mgt_txcharisk	mgt_txcharisk_array ( 2 downto 0 )
mgt_loopback_in	mgt_loopback_array ( 2 downto 0 )
mgt_rxchariscomma	mgt_rxchariskcomm_array ( 2 downto 0 )
mgt_rxcharisk	mgt_rxcharisk_array ( 2 downto 0 )
mgt_rxdisperr	mgt_rxdisperr_array ( 11 downto 0 )
mgt_rxnotintable	mgt_rxnotintable_array ( 11 downto 0 )
rxbyteisaligned	std_logic_vector ( 11 downto 0 )
mgt_rxcharisk_reg	std_logic_vector ( 47 downto 0 )
txcharisk	std_logic_vector ( 47 downto 0 )
reset	std_logic
rx_resetdone_i	std_logic_vector ( 11 downto 0 )
rx_disperr_i	std_logic_vector ( 47 downto 0 )
encode_error_i	std_logic_vector ( 47 downto 0 )
gt0_cpllfbclklost_out	std_logic_vector ( 0 downto 0 )
gt0_cplllock_out	std_logic_vector ( 0 downto 0 )
gt1_cpllfbclklost_out	std_logic_vector ( 0 downto 0 )
gt1_cplllock_out	std_logic_vector ( 0 downto 0 )
gt2_cpllfbclklost_out	std_logic_vector ( 0 downto 0 )
gt2_cplllock_out	std_logic_vector ( 0 downto 0 )
gt3_cpllfbclklost_out	std_logic_vector ( 0 downto 0 )
gt3_cplllock_out	std_logic_vector ( 0 downto 0 )

Instantiations
mgt_tx_rx_6g4	MGT_quad_gen <Entity MGT_quad_gen>
mgt_tx_rx_11g2	mgt11g2_tx_rx_cfpga_gen <Entity mgt11g2_tx_rx_cfpga_gen>

Detailed Description

Definition at line 90 of file top_mgt_cfpga.vhd.

---

The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd